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Added Proper Handshaking to Everything and Fixed a Couple of Bugs

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This commit is contained in:
felsabbagh3
2020-03-29 02:11:14 -07:00
parent d31b607e01
commit efac643c66
9 changed files with 523 additions and 627 deletions
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7
rtl/Vortex.v
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@@ -24,6 +24,8 @@ module Vortex
output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] dram_expected_lat,
input wire dram_req_delay,
// DRAM Dcache Res
output wire dram_fill_accept,
input wire dram_fill_rsp,
@@ -95,6 +97,7 @@ module Vortex
input wire [31:0] I_dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
input wire dram_req_delay,
input wire snp_req,
input wire [31:0] snp_req_addr,
@@ -140,6 +143,8 @@ module Vortex
assign dram_expected_lat = `DSIMULATED_DRAM_LATENCY_CYCLES;
assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept;
assign VX_gpu_dcache_dram_req.dram_req_delay = dram_req_delay;
genvar wordy;
generate
for (wordy = 0; wordy < `DBANK_LINE_SIZE_WORDS; wordy=wordy+1) begin
@@ -183,6 +188,8 @@ module Vortex
assign I_dram_expected_lat = `ISIMULATED_DRAM_LATENCY_CYCLES;
assign I_dram_fill_accept = VX_gpu_icache_dram_req.dram_fill_accept;
assign VX_gpu_icache_dram_req.dram_req_delay = dram_req_delay;
genvar iwordy;
generate
for (iwordy = 0; iwordy < `IBANK_LINE_SIZE_WORDS; iwordy=iwordy+1) begin