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Verilator testbench for unit tests

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This commit is contained in:
Blaise Tine
2021-03-24 09:53:10 -04:00
parent 4de75fad31
commit eee74a25cd
7 changed files with 178 additions and 259 deletions
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32
hw/unit_tests/cache/Makefile vendored
View File

@@ -1,46 +1,30 @@
PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4
TOP = VX_cache
PARAMS += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4
# control RTL debug print states
DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_CORE_DCACHE \
-DDBG_PRINT_CACHE_BANK \
-DDBG_PRINT_CACHE_SNP \
-DDBG_PRINT_CACHE_MSHR \
-DDBG_PRINT_CACHE_TAG \
-DDBG_PRINT_CACHE_DATA \
-DDBG_PRINT_DRAM \
-DDBG_PRINT_OPAE \
-DDBG_PRINT_AVS
#DBG_PRINT=$(DBG_PRINT_FLAGS)
INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs
INCLUDE = -I../../rtl/ -I../../rtl/libs -I../../rtl/cache
SRCS = cachesim.cpp testbench.cpp
all: build
CF += -std=c++11 -fms-extensions -I../..
CF += $(PARAMS)
VF += --language 1800-2009 --assert -Wall --trace #-Wpedantic
VF += -Wno-DECLFILENAME
VF += --x-initial unique
VF += -exe $(SRCS) $(INCLUDE)
DBG += -DVCD_OUTPUT $(DBG_PRINT)
VF += $(PARAMS)
gen:
verilator $(VF) -DNDEBUG -cc VX_cache.v $(PARAM) -CFLAGS '$(CF) -DNDEBUG $(PARAM)' --exe $(SRCS)
verilator $(VF) -cc $(TOP).v -CFLAGS '$(CF)' --exe $(SRCS)
build: gen
(cd obj_dir && make -j -f VVX_cache.mk)
(cd obj_dir && make -j -f V$(TOP).mk)
run: build
(cd obj_dir && ./VVX_cache)
(cd obj_dir && ./V$(TOP))
clean:
rm -rf obj_dir

10
hw/unit_tests/cache/cachesim.cpp vendored
View File

@@ -173,10 +173,10 @@ void CacheSim::stall_dram(){
}
void CacheSim::send_snoop_req(){
cache_->snp_req_valid = 1;
/*cache_->snp_req_valid = 1;
cache_->snp_req_addr = 0x12222222;
cache_->snp_req_invalidate = 1;
cache_->snp_req_tag = 0xff;
cache_->snp_req_tag = 0xff; */
}
void CacheSim::eval_dram_bus() {
@@ -274,9 +274,9 @@ bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){
//DEBUG
void CacheSim::display_miss(){
int i = (unsigned int)cache_->miss_vec;
std::bitset<8> x(i);
if (i) std::cout << "Miss Vec " << x << std::endl;
//int i = (unsigned int)cache_->miss_vec;
//std::bitset<8> x(i);
//if (i) std::cout << "Miss Vec " << x << std::endl;
//std::cout << "Miss Vec 0" << cache_->miss_vec[0] << std::endl;
}