wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

adding using serial divider to save area cost

Browse Source
This commit is contained in:
Blaise Tine
2020-08-25 02:29:27 -07:00
parent df25bae456
commit ee81e81818
10 changed files with 239 additions and 135 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
hw/rtl/VX_csr_data.v
View File

@@ -7,16 +7,16 @@ module VX_csr_data #(
input wire reset,
VX_cmt_to_csr_if cmt_to_csr_if,
VX_csr_to_issue_if csr_to_issue_if,
input wire[`NW_BITS-1:0] wid,
VX_csr_to_issue_if csr_to_issue_if,
input wire read_enable,
input wire[`CSR_ADDR_BITS-1:0] read_addr,
input wire[`NW_BITS-1:0] read_wid,
output wire[31:0] read_data,
input wire write_enable,
input wire[`CSR_ADDR_BITS-1:0] write_addr,
input wire[`NW_BITS-1:0] write_wid,
input wire[`CSR_WIDTH-1:0] write_data
);
reg [`CSR_WIDTH-1:0] csr_satp;
@@ -33,7 +33,7 @@ module VX_csr_data #(
reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0];
reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0];
reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
reg [31:0] read_data_r;
@@ -46,29 +46,32 @@ module VX_csr_data #(
if (write_enable) begin
case (write_addr)
`CSR_FFLAGS: begin
csr_fcsr[wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
csr_fflags[wid] <= write_data[`FFG_BITS-1:0];
csr_fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0];
end
`CSR_FRM: begin
csr_fcsr[wid][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
csr_frm[wid] <= write_data[`FRM_BITS-1:0];
csr_fcsr[write_wid][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
csr_frm[write_wid] <= write_data[`FRM_BITS-1:0];
end
`CSR_FCSR: begin
csr_fcsr[wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
csr_frm[wid] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS];
csr_fflags[wid] <= write_data[`FFG_BITS-1:0];
csr_fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
csr_frm[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS];
csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0];
end
`CSR_SATP: csr_satp <= write_data;
`CSR_SATP: csr_satp <= write_data;
`CSR_MSTATUS: csr_mstatus <= write_data;
`CSR_MEDELEG: csr_medeleg <= write_data;
`CSR_MIDELEG: csr_mideleg <= write_data;
`CSR_MIE: csr_mie <= write_data;
`CSR_MTVEC: csr_mtvec <= write_data;
`CSR_MIE: csr_mie <= write_data;
`CSR_MTVEC: csr_mtvec <= write_data;
`CSR_MEPC: csr_mepc <= write_data;
`CSR_MEPC: csr_mepc <= write_data;
`CSR_PMPCFG0: csr_pmpcfg[0] <= write_data;
`CSR_PMPCFG0: csr_pmpcfg[0] <= write_data;
`CSR_PMPADDR0: csr_pmpaddr[0] <= write_data;
default: begin
@@ -93,15 +96,15 @@ module VX_csr_data #(
always @(*) begin
read_data_r = 'x;
case (read_addr)
`CSR_FFLAGS : read_data_r = 32'(csr_fflags[wid]);
`CSR_FRM : read_data_r = 32'(csr_frm[wid]);
`CSR_FCSR : read_data_r = 32'(csr_fcsr[wid]);
`CSR_FFLAGS : read_data_r = 32'(csr_fflags[read_wid]);
`CSR_FRM : read_data_r = 32'(csr_frm[read_wid]);
`CSR_FCSR : read_data_r = 32'(csr_fcsr[read_wid]);
`CSR_LWID : read_data_r = 32'(wid);
`CSR_LWID : read_data_r = 32'(read_wid);
`CSR_LTID ,
`CSR_GTID ,
`CSR_MHARTID ,
`CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(wid);
`CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid);
`CSR_GCID : read_data_r = CORE_ID;
`CSR_NT : read_data_r = `NUM_THREADS;
`CSR_NW : read_data_r = `NUM_WARPS;