minor update
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@@ -25,20 +25,24 @@ module VX_gpu_unit #(
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_PARAM (CORE_ID)
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localparam WCTL_DATAW = `GPU_TMC_BITS + `GPU_WSPAWN_BITS + `GPU_SPLIT_BITS + `GPU_BARRIER_BITS;
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localparam RSP_DATAW = `MAX(`NUM_THREADS * 32, WCTL_DATAW);
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wire rsp_valid;
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wire rsp_valid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][31:0] rsp_data;
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wire [RSP_DATAW-1:0] rsp_data, rsp_data_r;
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gpu_tmc_t tmc;
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gpu_tmc_t tmc;
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gpu_wspawn_t wspawn;
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gpu_wspawn_t wspawn;
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gpu_barrier_t barrier;
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gpu_barrier_t barrier;
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gpu_split_t split;
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gpu_split_t split;
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wire [(`NUM_THREADS * 32)-1:0] warp_ctl_data;
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wire [WCTL_DATAW-1:0] warp_ctl_data;
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wire is_warp_ctl;
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wire is_warp_ctl;
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wire stall_in, stall_out;
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wire stall_in, stall_out;
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@@ -92,9 +96,7 @@ module VX_gpu_unit #(
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assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data[0] - 1);
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assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data[0] - 1);
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// pack warp ctl result
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// pack warp ctl result
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`IGNORE_WARNINGS_BEGIN
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assign warp_ctl_data = {tmc, wspawn, split, barrier};
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assign warp_ctl_data = {tmc, wspawn, barrier, split};
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`IGNORE_WARNINGS_END
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// texture
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// texture
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@@ -144,7 +146,7 @@ module VX_gpu_unit #(
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assign rsp_PC = tex_rsp_if.valid ? tex_rsp_if.PC : gpu_req_if.PC;
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assign rsp_PC = tex_rsp_if.valid ? tex_rsp_if.PC : gpu_req_if.PC;
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assign rsp_rd = tex_rsp_if.rd;
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assign rsp_rd = tex_rsp_if.rd;
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assign rsp_wb = tex_rsp_if.valid && tex_rsp_if.wb;
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assign rsp_wb = tex_rsp_if.valid && tex_rsp_if.wb;
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assign rsp_data = tex_rsp_if.valid ? tex_rsp_if.data : warp_ctl_data;
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assign rsp_data = tex_rsp_if.valid ? RSP_DATAW'(tex_rsp_if.data) : RSP_DATAW'(warp_ctl_data);
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`else
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`else
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@@ -163,7 +165,7 @@ module VX_gpu_unit #(
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assign rsp_PC = gpu_req_if.PC;
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assign rsp_PC = gpu_req_if.PC;
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assign rsp_rd = 0;
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assign rsp_rd = 0;
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assign rsp_wb = 0;
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assign rsp_wb = 0;
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assign rsp_data = warp_ctl_data;
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assign rsp_data = RSP_DATAW'(warp_ctl_data);
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`endif
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`endif
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@@ -173,23 +175,23 @@ module VX_gpu_unit #(
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assign stall_out = ~gpu_commit_if.ready && gpu_commit_if.valid;
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assign stall_out = ~gpu_commit_if.ready && gpu_commit_if.valid;
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VX_pipe_register #(
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + RSP_DATAW + 1),
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.RESETW (1)
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.RESETW (1)
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) pipe_reg (
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) pipe_reg (
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.enable (!stall_out),
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.enable (!stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data, is_warp_ctl}),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data, is_warp_ctl}),
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.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, gpu_commit_if.data, is_warp_ctl_r})
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.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, rsp_data_r, is_warp_ctl_r})
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);
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);
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assign gpu_commit_if.eop = 1'b1;
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assign gpu_commit_if.data = rsp_data_r[(`NUM_THREADS * 32)-1:0];
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assign gpu_commit_if.eop = 1'b1;
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// warp control reponse
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// warp control reponse
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`IGNORE_WARNINGS_BEGIN
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assign {warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier} = rsp_data_r[WCTL_DATAW-1:0];
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assign {warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.barrier, warp_ctl_if.split} = gpu_commit_if.data;
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`IGNORE_WARNINGS_END
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assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready && is_warp_ctl_r;
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assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready && is_warp_ctl_r;
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assign warp_ctl_if.wid = gpu_commit_if.wid;
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assign warp_ctl_if.wid = gpu_commit_if.wid;
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@@ -28,7 +28,7 @@ typedef struct packed {
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logic [`NUM_THREADS-1:0] tmask;
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logic [`NUM_THREADS-1:0] tmask;
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} gpu_tmc_t;
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} gpu_tmc_t;
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`define GPU_TMC_SIZE (1+`NUM_THREADS)
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`define GPU_TMC_BITS (1+`NUM_THREADS)
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typedef struct packed {
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typedef struct packed {
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logic valid;
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logic valid;
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@@ -36,7 +36,7 @@ typedef struct packed {
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logic [31:0] pc;
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logic [31:0] pc;
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} gpu_wspawn_t;
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} gpu_wspawn_t;
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`define GPU_WSPAWN_SIZE (1+`NUM_WARPS+32)
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`define GPU_WSPAWN_BITS (1+`NUM_WARPS+32)
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typedef struct packed {
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typedef struct packed {
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logic valid;
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logic valid;
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@@ -46,7 +46,7 @@ typedef struct packed {
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logic [31:0] pc;
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logic [31:0] pc;
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} gpu_split_t;
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} gpu_split_t;
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`define GPU_SPLIT_SIZE (1+1+`NUM_THREADS+`NUM_THREADS+32)
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`define GPU_SPLIT_BITS (1+1+`NUM_THREADS+`NUM_THREADS+32)
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typedef struct packed {
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typedef struct packed {
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logic valid;
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logic valid;
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@@ -54,6 +54,6 @@ typedef struct packed {
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logic [`NW_BITS-1:0] size_m1;
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logic [`NW_BITS-1:0] size_m1;
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} gpu_barrier_t;
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} gpu_barrier_t;
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`define GPU_BARRIER_SIZE (1+`NB_BITS+`NW_BITS)
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`define GPU_BARRIER_BITS (1+`NB_BITS+`NW_BITS)
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`endif
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`endif
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@@ -146,18 +146,12 @@
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"wsched_warp_pc": "32"
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"wsched_warp_pc": "32"
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},
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},
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"afu/vortex/cluster/core/pipeline/execute/gpu_unit": {
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"afu/vortex/cluster/core/pipeline/execute/gpu_unit": {
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"?gpu_req_fire": 1,
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"gpu_req_wid": "`NW_BITS",
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"gpu_req_tmask": "`NUM_THREADS",
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"gpu_req_op_type": "`GPU_BITS",
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"gpu_req_rs1": "32",
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"gpu_req_rs2": "32",
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"?gpu_rsp_valid": 1,
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"?gpu_rsp_valid": 1,
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"gpu_rsp_wid": "`NW_BITS",
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"gpu_rsp_wid": "`NW_BITS",
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"gpu_rsp_tmc": "`GPU_TMC_SIZE",
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"gpu_rsp_tmc": "`GPU_TMC_BITS",
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"gpu_rsp_wspawn": "`GPU_WSPAWN_SIZE",
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"gpu_rsp_wspawn": "`GPU_WSPAWN_BITS",
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"gpu_rsp_split": "`GPU_SPLIT_SIZE",
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"gpu_rsp_split": "`GPU_SPLIT_BITS",
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"gpu_rsp_barrier": "`GPU_BARRIER_SIZE"
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"gpu_rsp_barrier": "`GPU_BARRIER_BITS"
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},
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},
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"afu/vortex/cluster/core/pipeline/execute/lsu_unit": {
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"afu/vortex/cluster/core/pipeline/execute/lsu_unit": {
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"?dcache_req_fire":"`NUM_THREADS",
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"?dcache_req_fire":"`NUM_THREADS",
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@@ -240,7 +240,7 @@ def expand_text(text, params):
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iter = 0
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iter = 0
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while True:
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while True:
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if iter > 99:
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if iter > 65536:
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raise Exception("Macro recursion!")
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raise Exception("Macro recursion!")
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has_func = False
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has_func = False
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while True:
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while True:
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