Finished FE and BE high-level

rtl/interfaces/VX_csr_write_request_inter.v

@@ -0,0 +1,35 @@
+
+`include "VX_define.v"
+
+`ifndef VX_CSR_W_REQ
+
+`define VX_CSR_W_REQ
+
+interface VX_csr_write_request_inter ();
+
+		wire        is_csr;
+		wire[11:0]  csr_address;
+		/* verilator lint_off UNUSED */
+		wire[31:0]  csr_result;
+		/* verilator lint_on UNUSED */
+
+	// source-side view
+	modport snk (
+		input is_csr,
+		input csr_address,
+		input csr_result
+	);
+
+
+	// source-side view
+	modport src (
+		output is_csr,
+		output csr_address,
+		output csr_result
+	);
+
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_dcache_request_inter.v

@@ -0,0 +1,39 @@
+
+`include "VX_define.v"
+
+`ifndef VX_DCACHE_REQ
+
+`define VX_DCACHE_REQ
+
+interface VX_dcache_request_inter ();
+
+		wire[31:0] out_cache_driver_in_address[`NT_M1:0];
+		wire[2:0]  out_cache_driver_in_mem_read;
+		wire[2:0]  out_cache_driver_in_mem_write;
+		wire       out_cache_driver_in_valid[`NT_M1:0];
+		wire[31:0] out_cache_driver_in_data[`NT_M1:0];
+
+	// source-side view
+	modport snk (
+		input out_cache_driver_in_address,
+		input out_cache_driver_in_mem_read,
+		input out_cache_driver_in_mem_write,
+		input out_cache_driver_in_valid,
+		input out_cache_driver_in_data
+	);
+
+
+	// source-side view
+	modport src (
+		output out_cache_driver_in_address,
+		output out_cache_driver_in_mem_read,
+		output out_cache_driver_in_mem_write,
+		output out_cache_driver_in_valid,
+		output out_cache_driver_in_data
+	);
+
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_dcache_response_inter.v

@@ -0,0 +1,27 @@
+
+`include "VX_define.v"
+
+`ifndef VX_DCACHE_RSP
+
+`define VX_DCACHE_RSP
+
+interface VX_dcache_response_inter ();
+
+		wire[31:0]  in_cache_driver_out_data[`NT_M1:0];
+
+	// source-side view
+	modport snk (
+		input in_cache_driver_out_data
+	);
+
+
+	// source-side view
+	modport src (
+		output in_cache_driver_out_data
+	);
+
+
+endinterface
+
+
+`endif