minor update

2023-11-27 02:04:53 -08:00
parent 2f1171ca76
commit ebec982434
9 changed files with 15 additions and 15 deletions
--- a/hw/rtl/mem/VX_mem_arb.sv
+++ b/hw/rtl/mem/VX_mem_arb.sv
@@ -21,8 +21,8 @@ module VX_mem_arb #(
    parameter ADDR_WIDTH     = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)),
    parameter TAG_WIDTH      = 1,    
    parameter TAG_SEL_IDX    = 0,   
-    parameter OUT_REG_REQ   = 0,
-    parameter OUT_REG_RSP   = 0,
+    parameter OUT_REG_REQ    = 0,
+    parameter OUT_REG_RSP    = 0,
    parameter `STRING ARBITER = "R"
 ) (
    input wire              clk,