fixed msrq regression

hw/rtl/cache/VX_bank.v

@@ -505,14 +505,12 @@ module VX_bank #(
     wire miss_add_unqual = (miss_add_because_miss || miss_add_because_pending);
     assign mrvq_push_stall = miss_add_unqual && mrvq_full;
 
-
     wire miss_add = miss_add_unqual
                    && !mrvq_full 
                    && !(cwbq_push_stall 
                      || dwbq_push_stall 
                      || dram_fill_req_stall);  
 
-
     assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;  
 
     wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr  = addr_st2;

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -67,7 +67,7 @@ module VX_cache_miss_resrv #(
     `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
 
     assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
-    assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-1));
+    assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock
 
     wire                           enqueue_possible = !miss_resrv_full;
     wire [`LOG2UP(MRVQ_SIZE)-1:0]  enqueue_index    = tail_ptr;