fixed msrq regression

2020-06-03 17:22:24 -04:00
parent 9eb0389717
commit ea890b457d
2 changed files with 1 additions and 3 deletions
--- a/hw/rtl/cache/VX_cache_miss_resrv.v
+++ b/hw/rtl/cache/VX_cache_miss_resrv.v
@@ -67,7 +67,7 @@ module VX_cache_miss_resrv #(
    `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");

    assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
-    assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-1));
+    assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock

    wire                           enqueue_possible = !miss_resrv_full;
    wire [`LOG2UP(MRVQ_SIZE)-1:0]  enqueue_index    = tail_ptr;