wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

OUTPUT_REG refactoring

Browse Source
This commit is contained in:
Blaise Tine
2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
hw/rtl/libs/VX_dp_ram.v
View File

@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
@@ -24,7 +24,7 @@ module VX_dp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
@@ -93,7 +93,7 @@ module VX_dp_ram #(
end
end
end else begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin

20
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -1,10 +1,10 @@
`include "VX_platform.vh"
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter FASTRAM = 0
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
@@ -31,8 +31,8 @@ module VX_elastic_buffer #(
end else if (SIZE == 2) begin
VX_skid_buffer #(
.DATAW (DATAW),
.USE_FASTREG (BUFFERED)
.DATAW (DATAW),
.OUTPUT_REG (OUTPUT_REG)
) queue (
.clk (clk),
.reset (reset),
@@ -52,10 +52,10 @@ module VX_elastic_buffer #(
wire pop = valid_out && ready_out;
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),

40
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -1,14 +1,14 @@
`include "VX_platform.vh"
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter BUFFERED = 0,
parameter FASTRAM = 1
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0,
parameter FASTRAM = 1
) (
input wire clk,
input wire reset,
@@ -104,7 +104,7 @@ module VX_fifo_queue #(
if (SIZE == 2) begin
if (0 == BUFFERED) begin
if (0 == OUTPUT_REG) begin
reg [DATAW-1:0] shift_reg [1:0];
@@ -139,7 +139,7 @@ module VX_fifo_queue #(
end else begin
if (0 == BUFFERED) begin
if (0 == OUTPUT_REG) begin
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;
@@ -155,11 +155,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
@@ -200,11 +200,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),

4
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -4,7 +4,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter USE_FASTREG = 0
parameter OUTPUT_REG = 0
) (
input wire clk,
input wire reset,
@@ -50,7 +50,7 @@ module VX_skid_buffer #(
end else begin
if (USE_FASTREG) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;

20
hw/rtl/libs/VX_sp_ram.v
View File

@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
@@ -23,7 +23,7 @@ module VX_sp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
@@ -91,7 +91,7 @@ module VX_sp_ram #(
end
end
end else begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin

5
hw/rtl/libs/VX_stream_arbiter.v
View File

@@ -94,8 +94,9 @@ module VX_stream_arbiter #(
);
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),

5
hw/rtl/libs/VX_stream_demux.v
View File

@@ -39,8 +39,9 @@ module VX_stream_demux #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),