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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
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6
hw/rtl/generic_cache/VX_bank.v
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@@ -449,7 +449,7 @@ module VX_bank #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) vx_tag_data_access (
) tag_data_access (
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
@@ -477,7 +477,7 @@ module VX_bank #(
.miss_st1e (miss_st1e),
.dirty_st1e (dirty_st1e),
.fill_saw_dirty_st1e(fill_saw_dirty_st1e)
);
);
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
@@ -581,7 +581,7 @@ module VX_bank #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) vx_fill_invalidator (
) fill_invalidator (
.clk (clk),
.reset (reset),
.possible_fill (possible_fill),

8
hw/rtl/generic_cache/VX_cache.v
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@@ -157,7 +157,7 @@ module VX_cache #(
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
) vx_cache_dram_req_arb (
) cache_dram_req_arb (
.clk (clk),
.reset (reset),
.dfqq_full (dfqq_full),
@@ -191,7 +191,7 @@ module VX_cache #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
) vx_cache_core_req_bank_sell (
) cache_core_req_bank_sell (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids (per_bank_valids)
@@ -215,7 +215,7 @@ module VX_cache #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) vx_cache_core_wb_sel_merge (
) cache_core_wb_sel_merge (
.per_bank_wb_valid (per_bank_wb_valid),
.per_bank_wb_tid (per_bank_wb_tid),
.per_bank_wb_rd (per_bank_wb_rd),
@@ -239,7 +239,7 @@ module VX_cache #(
// Snoop Forward Logic
VX_snp_fwd_arb #(
.NUM_BANKS(NUM_BANKS)
) vx_snp_fwd_arb(
) snp_fwd_arb(
.per_bank_snp_fwd (per_bank_snp_fwd),
.per_bank_snp_fwd_addr(per_bank_snp_fwd_addr),
.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),

2
hw/rtl/generic_cache/VX_cache_dfq_queue.v
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@@ -94,7 +94,7 @@ module VX_cache_dfq_queue #(
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_bank (
) sel_bank (
.valids(qual_bank_dram_fill_req),
.index (qual_request_index),
.found (qual_has_request)

4
hw/rtl/generic_cache/VX_cache_dram_req_arb.v
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@@ -102,7 +102,7 @@ module VX_cache_dram_req_arb #(
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req_valid);
VX_cache_dfq_queue vx_cache_dfq_queue(
VX_cache_dfq_queue cache_dfq_queue(
.clk (clk),
.reset (reset),
.dfqq_push (dfqq_push),
@@ -121,7 +121,7 @@ module VX_cache_dram_req_arb #(
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_dwb (
) sel_dwb (
.valids(use_wb_valid),
.index (dwb_bank),
.found (dwb_valid)

5
hw/rtl/generic_cache/VX_cache_req_queue.v
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@@ -142,10 +142,11 @@ module VX_cache_req_queue #(
assign qual_pc = use_per_pc;
wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
wire qual_has_request;
VX_generic_priority_encoder #(
.N(NUM_REQUESTS)
) vx_sel_bank (
) sel_bank (
.valids(qual_valids),
.index (qual_request_index),
.found (qual_has_request)

2
hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
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@@ -80,7 +80,7 @@ module VX_cache_wb_sel_merge #(
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_bank (
) sel_bank (
.valids(per_bank_wb_valid),
.index (main_bank_index),
.found (found_bank)

30
hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v
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@@ -1,7 +1,6 @@
`include "VX_cache_config.vh"
module VX_dcache_llv_resp_bank_sel
#(
module VX_dcache_llv_resp_bank_sel #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
@@ -15,8 +14,7 @@ module VX_dcache_llv_resp_bank_sel
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
@@ -26,7 +24,7 @@ module VX_dcache_llv_resp_bank_sel
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
@@ -39,12 +37,9 @@ module VX_dcache_llv_resp_bank_sel
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
) (
output reg [NUM_BANKS-1:0] per_bank_llvq_pop,
input wire[NUM_BANKS-1:0] per_bank_llvq_valid,
input wire[NUM_BANKS-1:0][31:0] per_bank_llvq_rsp_addr,
@@ -55,20 +50,19 @@ module VX_dcache_llv_resp_bank_sel
output reg[NUM_REQUESTS-1:0] llvq_valid,
output reg[NUM_REQUESTS-1:0][31:0] llvq_rsp_addr,
output reg[NUM_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_rsp_data
);
wire [(`LOG2UP(NUM_BANKS))-1:0] main_bank_index;
wire found_bank;
wire found_bank;
VX_generic_priority_encoder #(.N(NUM_BANKS)) vx_sel_bank(
.valids(per_bank_llvq_valid),
.index (main_bank_index),
.found (found_bank)
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank(
.valids(per_bank_llvq_valid),
.index (main_bank_index),
.found (found_bank)
);
always @(*) begin
llvq_valid = 0;
llvq_rsp_addr = 0;

4
hw/rtl/generic_cache/VX_fill_invalidator.v
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@@ -86,7 +86,7 @@ module VX_fill_invalidator
VX_generic_priority_encoder #(
.N(FILL_INVALIDAOR_SIZE)
) vx_sel_bank (
) sel_bank (
.valids(~fills_active),
.index (enqueue_index),
.found (enqueue_found)
@@ -136,7 +136,7 @@ module VX_fill_invalidator
// wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) vx_sel_bank(
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)

2
hw/rtl/generic_cache/VX_snp_fwd_arb.v
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@@ -22,7 +22,7 @@ module VX_snp_fwd_arb
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) vx_sel_ffsq(
) sel_ffsq (
.valids(qual_per_bank_snp_fwd),
.index (fsq_bank),
.found (fsq_valid)

2
hw/rtl/generic_cache/VX_tag_data_access.v
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@@ -110,7 +110,7 @@ module VX_tag_data_access #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) vx_tag_data_structure (
) tag_data_structure (
.clk (clk),
.reset (reset),
.stall_bank_pipe(stall_bank_pipe),