wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

RTL code refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-04-19 09:24:04 -04:00
parent 3139d37610
commit e9dfa828fe
33 changed files with 998 additions and 1022 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
hw/rtl/VX_writeback.v
View File

@@ -1,67 +1,66 @@
`include "VX_define.vh"
module VX_writeback (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Mem WB info
VX_inst_mem_wb_if vx_mem_wb,
VX_inst_mem_wb_if mem_wb_if,
// EXEC Unit WB info
VX_inst_exec_wb_if vx_inst_exec_wb,
VX_inst_exec_wb_if inst_exec_wb_if,
// CSR Unit WB info
VX_csr_wb_if vx_csr_wb,
VX_csr_wb_if csr_wb_if,
// Actual WB to GPR
VX_wb_if vx_writeback_if,
output wire no_slot_mem,
output wire no_slot_exec,
output wire no_slot_csr
VX_wb_if writeback_if,
output wire no_slot_mem,
output wire no_slot_exec,
output wire no_slot_csr
);
VX_wb_if vx_writeback_tempp();
VX_wb_if writeback_tempp_if();
wire exec_wb = (vx_inst_exec_wb.wb != 0) && (|vx_inst_exec_wb.wb_valid);
wire mem_wb = (vx_mem_wb.wb != 0) && (|vx_mem_wb.wb_valid);
wire csr_wb = (vx_csr_wb.wb != 0) && (|vx_csr_wb.valid);
wire exec_wb = (inst_exec_wb_if.wb != 0) && (|inst_exec_wb_if.wb_valid);
wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.wb_valid);
wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign no_slot_exec = 0;
assign vx_writeback_tempp.write_data = exec_wb ? vx_inst_exec_wb.alu_result :
csr_wb ? vx_csr_wb.csr_result :
mem_wb ? vx_mem_wb.loaded_data :
assign writeback_tempp_if.write_data = exec_wb ? inst_exec_wb_if.alu_result :
csr_wb ? csr_wb_if.csr_result :
mem_wb ? mem_wb_if.loaded_data :
0;
assign vx_writeback_tempp.wb_valid = exec_wb ? vx_inst_exec_wb.wb_valid :
csr_wb ? vx_csr_wb.valid :
mem_wb ? vx_mem_wb.wb_valid :
assign writeback_tempp_if.wb_valid = exec_wb ? inst_exec_wb_if.wb_valid :
csr_wb ? csr_wb_if.valid :
mem_wb ? mem_wb_if.wb_valid :
0;
assign vx_writeback_tempp.rd = exec_wb ? vx_inst_exec_wb.rd :
csr_wb ? vx_csr_wb.rd :
mem_wb ? vx_mem_wb.rd :
assign writeback_tempp_if.rd = exec_wb ? inst_exec_wb_if.rd :
csr_wb ? csr_wb_if.rd :
mem_wb ? mem_wb_if.rd :
0;
assign vx_writeback_tempp.wb = exec_wb ? vx_inst_exec_wb.wb :
csr_wb ? vx_csr_wb.wb :
mem_wb ? vx_mem_wb.wb :
assign writeback_tempp_if.wb = exec_wb ? inst_exec_wb_if.wb :
csr_wb ? csr_wb_if.wb :
mem_wb ? mem_wb_if.wb :
0;
assign vx_writeback_tempp.wb_warp_num = exec_wb ? vx_inst_exec_wb.wb_warp_num :
csr_wb ? vx_csr_wb.warp_num :
mem_wb ? vx_mem_wb.wb_warp_num :
assign writeback_tempp_if.wb_warp_num = exec_wb ? inst_exec_wb_if.wb_warp_num :
csr_wb ? csr_wb_if.warp_num :
mem_wb ? mem_wb_if.wb_warp_num :
0;
assign vx_writeback_tempp.wb_pc = exec_wb ? vx_inst_exec_wb.exec_wb_pc :
assign writeback_tempp_if.wb_pc = exec_wb ? inst_exec_wb_if.exec_wb_pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? vx_mem_wb.mem_wb_pc :
mem_wb ? mem_wb_if.mem_wb_pc :
32'hdeadbeef;
wire zero = 0;
wire[`NUM_THREADS-1:0][31:0] use_wb_data;
@@ -71,19 +70,19 @@ module VX_writeback (
.reset(reset),
.stall(zero),
.flush(zero),
.in ({vx_writeback_tempp.write_data, vx_writeback_tempp.wb_valid, vx_writeback_tempp.rd, vx_writeback_tempp.wb, vx_writeback_tempp.wb_warp_num, vx_writeback_tempp.wb_pc}),
.out ({use_wb_data , vx_writeback_if.wb_valid, vx_writeback_if.rd, vx_writeback_if.wb, vx_writeback_if.wb_warp_num, vx_writeback_if.wb_pc})
.in ({writeback_tempp_if.write_data, writeback_tempp_if.wb_valid, writeback_tempp_if.rd, writeback_tempp_if.wb, writeback_tempp_if.wb_warp_num, writeback_tempp_if.wb_pc}),
.out ({use_wb_data , writeback_if.wb_valid, writeback_if.rd, writeback_if.wb, writeback_if.wb_warp_num, writeback_if.wb_pc})
);
reg[31:0] last_data_wb /* verilator public */ ;
always @(posedge clk) begin
if ((|vx_writeback_if.wb_valid) && (vx_writeback_if.wb != 0) && (vx_writeback_if.rd == 28)) begin
if ((|writeback_if.wb_valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
last_data_wb <= use_wb_data[0];
end
end
assign vx_writeback_if.write_data = use_wb_data;
assign writeback_if.write_data = use_wb_data;
endmodule : VX_writeback