RTL code refactoring
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@@ -1,7 +1,7 @@
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module VX_csr_handler (
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input wire clk,
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input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done
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VX_csr_write_request_if vx_csr_w_req,
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VX_csr_write_request_if csr_w_req_if,
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input wire in_wb_valid,
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output wire[31:0] out_decode_csr_data // done
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);
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@@ -9,9 +9,9 @@ module VX_csr_handler (
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wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address;
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wire[31:0] in_mem_csr_result;
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assign in_mem_is_csr = vx_csr_w_req.is_csr;
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assign in_mem_csr_address = vx_csr_w_req.csr_address;
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assign in_mem_csr_result = vx_csr_w_req.csr_result;
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assign in_mem_is_csr = csr_w_req_if.is_csr;
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assign in_mem_csr_address = csr_w_req_if.csr_address;
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assign in_mem_csr_result = csr_w_req_if.csr_result;
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reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0];
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