SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

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wgulian3

2020-01-24 06:08:00 -05:00

parent 60f0cfe215

commit e9cdc6e5af

18 changed files with 1665 additions and 66 deletions

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rtl/quartus/VX_gpr_syn.qsf

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