SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:08:00 -05:00
parent 60f0cfe215
commit e9cdc6e5af
18 changed files with 1665 additions and 66 deletions
--- a/rtl/VX_warp.v
+++ b/rtl/VX_warp.v
@@ -49,8 +49,9 @@ module VX_warp (

 		genvar out_cur_th;
 		generate
-			for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
+			for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) begin : out_valid_assign
 				assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0  : valid[out_cur_th];
+			end
 		endgenerate