regression fixes

This commit is contained in:
Blaise Tine
2021-06-29 04:32:32 -04:00
parent 5095836bd2
commit e8c01e18d8
15 changed files with 67 additions and 231 deletions

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@@ -8,7 +8,17 @@ all:
$(MAKE) -C printf
$(MAKE) -C psort
run:
run-simx:
$(MAKE) -C vecadd run-simx
$(MAKE) -C sgemm run-simx
$(MAKE) -C saxpy run-simx
$(MAKE) -C sfilter run-simx
$(MAKE) -C nearn run-simx
$(MAKE) -C guassian run-simx
$(MAKE) -C printf run-simx
#$(MAKE) -C psort run-simx
run-vlsim:
$(MAKE) -C vecadd run-vlsim
$(MAKE) -C sgemm run-vlsim
$(MAKE) -C saxpy run-vlsim
@@ -16,7 +26,7 @@ run:
$(MAKE) -C nearn run-vlsim
$(MAKE) -C guassian run-vlsim
$(MAKE) -C printf run-vlsim
#$(MAKE) -C psort run-vlsim
#$(MAKE) -C psort run-vlsim
clean:
$(MAKE) -C vecadd clean

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@@ -8,7 +8,17 @@ all:
$(MAKE) -C diverge
$(MAKE) -C fence
run:
run-simx:
$(MAKE) -C basic run-simx
$(MAKE) -C demo run-simx
$(MAKE) -C dogfood run-simx
$(MAKE) -C mstress run-simx
$(MAKE) -C io_addr run-simx
$(MAKE) -C printf run-simx
$(MAKE) -C diverge run-simx
$(MAKE) -C fence run-simx
run-vlsim:
$(MAKE) -C basic run-vlsim
$(MAKE) -C demo run-vlsim
$(MAKE) -C dogfood run-vlsim

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@@ -1,6 +1,9 @@
all:
run:
$(MAKE) -C isa run
run-simx:
$(MAKE) -C isa run-simx
run-rtlsim:
$(MAKE) -C isa run-rtlsim
clean:

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@@ -1,8 +1,13 @@
TESTS := $(wildcard *.hex)
ALL_TESTS := $(wildcard *.hex)
VTESTS := $(wildcard *-v-*.hex)
V_TESTS := $(wildcard *-v-*.hex)
TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS))
EXCLUDED_TESTS := $(V_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
run:
cd ../../../hw/simulate/obj_dir && ./VVortex -r $(foreach test,$(TESTS),../../../tests/riscv/isa/$(test))
TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS))
run-simx:
$(foreach test,$(TESTS), ../../../simX/simX -r -a rv32i -c 1 -i $(test);)
run-rtlsim:
$(foreach test,$(TESTS), ../../../hw/simulate/obj_dir/VVortex -r $(test);)

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@@ -3,10 +3,15 @@ all:
$(MAKE) -C fibonacci
$(MAKE) -C simple
run:
$(MAKE) -C hello run
$(MAKE) -C fibonacci run
$(MAKE) -C simple run
run-simx:
$(MAKE) -C hello run-simx
$(MAKE) -C fibonacci run-simx
$(MAKE) -C simple run-simx
run-rtlsim:
$(MAKE) -C hello run-rtlsim
$(MAKE) -C fibonacci run-rtlsim
$(MAKE) -C simple run-rtlsim
clean:
$(MAKE) -C hello clean

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@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
$(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex
run-rtlsim: $(PROJECT).hex
../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
run-simx: $(PROJECT).hex
../../../simX/simX -a rv32i -i $(PROJECT).hex
../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
.depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend;

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@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
$(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex
run-rtlsim: $(PROJECT).hex
../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
run-simx: $(PROJECT).hex
../../../simX/simX -a rv32i -i $(PROJECT).hex
../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
.depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend;

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@@ -26,11 +26,11 @@ $(PROJECT).hex: $(PROJECT).elf
$(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex
run-rtlsim: $(PROJECT).hex
../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex
run-simx: $(PROJECT).hex
../../../simX/simX -a rv32i -i $(PROJECT).hex
../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex
.depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend;