RTL code refactoring

hw/syn/quartus/top/Makefile

@@ -57,7 +57,7 @@ smart.log: $(PROJECT_FILES)
 
 # Project initialization
 $(PROJECT_FILES):
-	$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../generic_cache;../shared_memory;../compat"
+	$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache;../shared_memory"
 	
 syn.chg:
 	$(STAMP) syn.chg

hw/syn/quartus/vx_cache/Makefile

@@ -1,6 +1,6 @@
 PROJECT = VX_cache
 TOP_LEVEL_ENTITY = VX_cache
-SRC_FILE = ../../../rtl/generic_cache/VX_cache.v
+SRC_FILE = ../../../rtl/cache/VX_cache.v
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 QUARTUS_ROOT ?= /tools/reconfig/intel/18.0

hw/syn/yosys/diagram.ys

@@ -1,5 +1,5 @@
 # load design
-read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v
+read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs  ../../rtl/Vortex.v
 
 # dump diagram
 show

hw/syn/yosys/synthesis.ys

@@ -1,5 +1,5 @@
 # load design
-read_verilog -sv -I../../rtl -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/generic_cache -I../../rtl/shared_memory -I../../rtl/pipe_regs -I../../rtl/compat ../../rtl/Vortex.v
+read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs  ../../rtl/Vortex.v
 
 # high-level synthesis
 proc; opt; fsm;; memory -nomap; opt