RTL code refactoring

This commit is contained in:
Blaise Tine
2020-04-20 12:09:30 -04:00
parent e8072bab77
commit e8a4923eb4
53 changed files with 79 additions and 1988 deletions

View File

@@ -0,0 +1,20 @@
`include "VX_define.vh"
module VX_priority_encoder (
input wire[`NUM_WARPS-1:0] valids,
output reg[`NW_BITS-1:0] index,
output reg found
);
integer i;
always @(*) begin
index = 0;
found = 0;
for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
index = i[`NW_BITS-1:0];
found = 1;
end
end
end
endmodule