From e82e29c855822ea0b98351bedc72cd8b0b3f21a8 Mon Sep 17 00:00:00 2001
From: codetector <codetector@codetector.cn>
Date: Wed, 19 Feb 2020 23:19:05 -0500
Subject: [PATCH] remove async reset for FPGA synthesis

---
 rtl/cache/VX_cache_data.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v
index 62c62bd9..b4aac41e 100644
--- a/rtl/cache/VX_cache_data.v
+++ b/rtl/cache/VX_cache_data.v
@@ -79,10 +79,10 @@ module VX_cache_data
         always @(posedge clk, posedge rst) begin : update_all
           if (rst) begin
             for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin
-                data[ini_ind]  <= 0;
-                tag[ini_ind]   <= 0;
+                //data[ini_ind]  <= 0;
+                //tag[ini_ind]   <= 0;
                 valid[ini_ind] <= 0;
-                dirty[ini_ind] <= 0;
+                //dirty[ini_ind] <= 0;
             end
           end else begin
               if (update_dirty) dirty[addr] <= dirt_new; // WRite Port