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missing rtl changes from OPAE

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This commit is contained in:
Blaise Tine
2020-03-27 22:37:35 -04:00
parent 550d96a73c
commit e80fa7f233
8 changed files with 160 additions and 149 deletions
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44
rtl/Makefile
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@@ -1,32 +1,35 @@
all: RUNFILE all: RUNFILE
INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
SINGLE_CORE=Vortex.v SINGLE_CORE = Vortex.v
MULTI_CORE=Vortex_SOC.v
EXE=--exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp MULTI_CORE = Vortex_SOC.v
MULTI_EXE=--exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
COMP=--compiler gcc --language 1800-2009 EXE += --exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN MULTI_EXE += --exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
VF += -compiler gcc --language 1800-2009
WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO= # WNO=
# LIGHTW= # LIGHTW=
LIGHTW=-Wno-UNOPTFLAT LIGHTW += -Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/' # LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB= LIB +=
CF = -std=c++11 -fms-extensions CF += -std=c++11 -fms-extensions
DEB=--trace -DVL_DEBUG=1 DEB += --trace -DVL_DEBUG=1
MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk) MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk)
MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1) MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
@@ -36,23 +39,22 @@ build_config:
# -LDFLAGS '-lsystemc' # -LDFLAGS '-lsystemc'
VERILATOR: build_config VERILATOR: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW) verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW)
VERILATORnoWarnings: build_config VERILATORnoWarnings: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB)
VERILATORnoWarningsRel: build_config VERILATORnoWarningsRel: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS) verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
VERILATORMULTInoWarnings: build_config VERILATORMULTInoWarnings: build_config
verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB) verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS)
compdebug: build_config compdebug: build_config
verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
compdebugmulti: build_config compdebugmulti: build_config
verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB) verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
RUNFILE: VERILATOR RUNFILE: VERILATOR
$(MAKECPP) $(MAKECPP)

22
rtl/Vortex.v
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@@ -30,11 +30,31 @@ module Vortex
input wire [31:0] dram_fill_rsp_addr, input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// LLC Snooping // DRAM Icache Req
output wire I_dram_req,
output wire I_dram_req_write,
output wire I_dram_req_read,
output wire [31:0] I_dram_req_addr,
output wire [31:0] I_dram_req_size,
output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG],
output wire [31:0] I_dram_expected_lat,
// DRAM Icache Res
output wire I_dram_fill_accept,
input wire I_dram_fill_rsp,
input wire [31:0] I_dram_fill_rsp_addr,
input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG],
// Dcache Snooping
input wire snp_req, input wire snp_req,
input wire [31:0] snp_req_addr, input wire [31:0] snp_req_addr,
output wire snp_req_delay, output wire snp_req_delay,
// Icache Snooping
input wire I_snp_req,
input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay,
output wire out_ebreak output wire out_ebreak
`else `else

8
rtl/Vortex_SOC.v
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@@ -369,11 +369,11 @@ module Vortex_SOC (
assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core]; assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1]; assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd; assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr; assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
end end
// endgenerate // endgenerate

5
rtl/shared_memory/VX_shared_memory_block.v
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@@ -29,6 +29,8 @@ module VX_shared_memory_block
`ifndef SYN `ifndef SYN
reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0];
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
//wire need_to_write = (|we); //wire need_to_write = (|we);
integer curr_ind; integer curr_ind;
@@ -48,8 +50,7 @@ module VX_shared_memory_block
if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3]; if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3];
end end
end end
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
assign reg_addr = addr; assign reg_addr = addr;
// always @(posedge clk) // always @(posedge clk)
// reg_addr <= addr; // reg_addr <= addr;

109
rtl/simulate/Vortex.h
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@@ -1,7 +1,7 @@
// C++ libraries // C++ libraries
#include <utility> #include <utility>
#include <iostream> #include <iostream>
#include <map> #include <map>
#include <iterator> #include <iterator>
#include <iomanip> #include <iomanip>
#include <fstream> #include <fstream>
@@ -20,62 +20,61 @@
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#endif #endif
typedef struct typedef struct {
{ int cycles_left;
int cycles_left; int data_length;
int data_length; unsigned base_addr;
unsigned base_addr; unsigned *data;
unsigned * data;
} dram_req_t; } dram_req_t;
class Vortex class Vortex {
{ public:
public: Vortex(RAM *ram);
Vortex(RAM* ram); ~Vortex();
~Vortex(); bool is_busy();
bool simulate(); void reset();
void step(); void step();
void reset(); void flush_caches(uint32_t mem_addr, uint32_t size);
void flush_caches(uint32_t mem_addr, uint32_t size); bool simulate();
bool is_busy();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM* ram; private:
void print_stats(bool cycle_test = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
VVortex * vortex; RAM *ram;
unsigned start_pc; VVortex *vortex;
bool refill_d;
unsigned refill_addr_d; unsigned start_pc;
bool refill_i; bool refill_d;
unsigned refill_addr_i; unsigned refill_addr_d;
long int curr_cycle; bool refill_i;
bool stop; unsigned refill_addr_i;
bool unit_test; long int curr_cycle;
std::ofstream results; bool stop;
int stats_static_inst; bool unit_test;
int stats_dynamic_inst; std::ofstream results;
int stats_total_cycles; int stats_static_inst;
int stats_fwd_stalls; int stats_dynamic_inst;
int stats_branch_stalls; int stats_total_cycles;
int debug_state; int stats_fwd_stalls;
int ibus_state; int stats_branch_stalls;
int dbus_state; int debug_state;
int debug_return; int ibus_state;
int debug_wait_num; int dbus_state;
int debug_inst_num; int debug_return;
int debug_end_wait; int debug_wait_num;
int debug_debugAddr; int debug_inst_num;
double stats_sim_time; int debug_end_wait;
std::vector<dram_req_t> dram_req_vec; int debug_debugAddr;
std::vector<dram_req_t> I_dram_req_vec; double stats_sim_time;
#ifdef VCD_OUTPUT std::vector<dram_req_t> dram_req_vec;
VerilatedVcdC *m_trace; std::vector<dram_req_t> I_dram_req_vec;
#endif #ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
}; };

108
rtl/simulate/Vortex_SOC.h
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@@ -1,7 +1,7 @@
// C++ libraries // C++ libraries
#include <utility> #include <utility>
#include <iostream> #include <iostream>
#include <map> #include <map>
#include <iterator> #include <iterator>
#include <iomanip> #include <iomanip>
#include <fstream> #include <fstream>
@@ -19,61 +19,59 @@
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#endif #endif
typedef struct typedef struct {
{ int cycles_left;
int cycles_left; int data_length;
int data_length; unsigned base_addr;
unsigned base_addr; unsigned *data;
unsigned * data;
} dram_req_t; } dram_req_t;
class Vortex_SOC class Vortex_SOC {
{ public:
public: Vortex_SOC(RAM *ram);
Vortex_SOC(RAM* ram); ~Vortex_SOC();
~Vortex_SOC(); bool is_busy();
bool simulate(); void reset();
void step(); void step();
void reset(); void flush_caches(uint32_t mem_addr, uint32_t size);
void flush_caches(uint32_t mem_addr, uint32_t size); bool simulate();
bool is_busy(); private:
private: void print_stats(bool cycle_test = true);
void print_stats(bool = true); bool ibus_driver();
bool ibus_driver(); bool dbus_driver();
bool dbus_driver(); void io_handler();
void io_handler(); void send_snoops(uint32_t mem_addr, uint32_t size);
void send_snoops(uint32_t mem_addr, uint32_t size); void wait(uint32_t cycles);
void wait(uint32_t cycles);
RAM* ram; RAM *ram;
VVortex_SOC * vortex; VVortex_SOC *vortex;
unsigned start_pc; unsigned start_pc;
bool refill_d; bool refill_d;
unsigned refill_addr_d; unsigned refill_addr_d;
bool refill_i; bool refill_i;
unsigned refill_addr_i; unsigned refill_addr_i;
long int curr_cycle; long int curr_cycle;
bool stop; bool stop;
bool unit_test; bool unit_test;
std::ofstream results; std::ofstream results;
int stats_static_inst; int stats_static_inst;
int stats_dynamic_inst; int stats_dynamic_inst;
int stats_total_cycles; int stats_total_cycles;
int stats_fwd_stalls; int stats_fwd_stalls;
int stats_branch_stalls; int stats_branch_stalls;
int debug_state; int debug_state;
int ibus_state; int ibus_state;
int dbus_state; int dbus_state;
int debug_return; int debug_return;
int debug_wait_num; int debug_wait_num;
int debug_inst_num; int debug_inst_num;
int debug_end_wait; int debug_end_wait;
int debug_debugAddr; int debug_debugAddr;
double stats_sim_time; double stats_sim_time;
std::vector<dram_req_t> dram_req_vec; std::vector<dram_req_t> dram_req_vec;
#ifdef VCD_OUTPUT #ifdef VCD_OUTPUT
VerilatedVcdC *m_trace; VerilatedVcdC *m_trace;
#endif #endif
}; };

8
rtl/simulate/multi_test_bench.cpp
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@@ -3,16 +3,10 @@
#define NUM_TESTS 46 #define NUM_TESTS 46
int main(int argc, char **argv) int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true); #define ALL_TESTS
// #define ALL_TESTS
#ifdef ALL_TESTS #ifdef ALL_TESTS
bool passed = true; bool passed = true;
std::string tests[NUM_TESTS] = { std::string tests[NUM_TESTS] = {

5
rtl/simulate/test_bench.cpp
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@@ -9,10 +9,7 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true); #define ALL_TESTS
// #define ALL_TESTS
#ifdef ALL_TESTS #ifdef ALL_TESTS
bool passed = true; bool passed = true;