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minor update

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This commit is contained in:
Blaise Tine
2021-08-05 11:49:05 -07:00
parent 43ad188ccb
commit e7aa93614b
14 changed files with 1728 additions and 1574 deletions
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28
hw/rtl/tex_unit/VX_tex_addr.v
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@@ -1,9 +1,9 @@
`include "VX_tex_define.vh"
module VX_tex_addr #(
parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1,
parameter NUM_REQS = 1
parameter CORE_ID = 0,
parameter REQ_INFOW = 1,
parameter NUM_REQS = 1
) (
input wire clk,
input wire reset,
@@ -19,7 +19,7 @@ module VX_tex_addr #(
input wire [`TEX_ADDR_BITS-1:0] req_baseaddr,
input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,
input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,
input wire [REQ_INFO_WIDTH-1:0] req_info,
input wire [REQ_INFOW-1:0] req_info,
output wire req_ready,
// outputs
@@ -30,7 +30,7 @@ module VX_tex_addr #(
output wire [`TEX_STRIDE_BITS-1:0] rsp_stride,
output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
output wire [REQ_INFOW-1:0] rsp_info,
input wire rsp_ready
);
@@ -38,10 +38,10 @@ module VX_tex_addr #(
localparam PITCH_BITS = `ADDER_CARRY_WIDTH(`TEX_DIM_BITS, `TEX_STRIDE_BITS);
wire valid_s0;
wire [NUM_REQS-1:0] tmask_s0;
wire valid_s0;
wire [NUM_REQS-1:0] tmask_s0;
wire [`TEX_FILTER_BITS-1:0] filter_s0;
wire [REQ_INFO_WIDTH-1:0] req_info_s0;
wire [REQ_INFOW-1:0] req_info_s0;
wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_lo, clamped_lo_s0;
wire [NUM_REQS-1:0][1:0][`FIXED_FRAC-1:0] clamped_hi, clamped_hi_s0;
wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;
@@ -90,7 +90,7 @@ module VX_tex_addr #(
end
VX_pipe_register #(
.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFO_WIDTH + NUM_REQS * (PITCH_BITS + `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),
.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFOW + NUM_REQS * (PITCH_BITS + `TEX_DIM_BITS + 32 + 2 * 2 * `FIXED_FRAC)),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
@@ -127,7 +127,7 @@ module VX_tex_addr #(
assign stall_out = rsp_valid && ~rsp_ready;
VX_pipe_register #(
.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFO_WIDTH),
.DATAW (1 + NUM_REQS + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (NUM_REQS * 4 * 32) + (2 * NUM_REQS * `BLEND_FRAC) + REQ_INFOW),
.RESETW (1)
) pipe_reg1 (
.clk (clk),
@@ -157,18 +157,18 @@ module VX_tex_addr #(
function logic [(`FIXED_INT+`TEX_STRIDE_BITS)-1:0] scale_to_pitch (input logic [`FIXED_FRAC-1:0] src,
input logic [PITCH_BITS-1:0] dim);
`IGNORE_UNUSED_BEGIN
`IGNORE_WARNINGS_BEGIN
logic [(`FIXED_BITS+`TEX_STRIDE_BITS)-1:0] out;
`IGNORE_UNUSED_END
`IGNORE_WARNINGS_END
out = (`FIXED_BITS+`TEX_STRIDE_BITS)'(src) << dim;
return out[`FIXED_FRAC +: (`FIXED_INT+`TEX_STRIDE_BITS)];
endfunction
function logic [`FIXED_INT-1:0] scale_to_height (input logic [`FIXED_FRAC-1:0] src,
input logic [`TEX_DIM_BITS-1:0] dim);
`IGNORE_UNUSED_BEGIN
`IGNORE_WARNINGS_BEGIN
logic [`FIXED_BITS-1:0] out;
`IGNORE_UNUSED_END
`IGNORE_WARNINGS_END
out = `FIXED_BITS'(src) << dim;
return out[`FIXED_FRAC +: `FIXED_INT];
endfunction

28
hw/rtl/tex_unit/VX_tex_memory.v
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@@ -1,8 +1,8 @@
`include "VX_tex_define.vh"
module VX_tex_memory #(
parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1,
parameter NUM_REQS = 1
parameter CORE_ID = 0,
parameter REQ_INFOW = 1,
parameter NUM_REQS = 1
) (
input wire clk,
input wire reset,
@@ -17,14 +17,14 @@ module VX_tex_memory #(
input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [`TEX_STRIDE_BITS-1:0] req_stride,
input wire [NUM_REQS-1:0][3:0][31:0] req_addr,
input wire [REQ_INFO_WIDTH-1:0] req_info,
input wire [REQ_INFOW-1:0] req_info,
output wire req_ready,
// outputs
output wire rsp_valid,
output wire [NUM_REQS-1:0] rsp_tmask,
output wire [NUM_REQS-1:0][3:0][31:0] rsp_data,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
output wire [REQ_INFOW-1:0] rsp_info,
input wire rsp_ready
);
@@ -59,18 +59,18 @@ module VX_tex_memory #(
wire reqq_push, reqq_pop, reqq_empty, reqq_full;
wire [3:0][NUM_REQS-1:0][29:0] q_req_addr;
wire [NUM_REQS-1:0] q_req_tmask;
wire [`TEX_FILTER_BITS-1:0] q_req_filter;
wire [REQ_INFO_WIDTH-1:0] q_req_info;
wire [`TEX_STRIDE_BITS-1:0] q_req_stride;
wire [3:0][NUM_REQS-1:0][1:0] q_align_offs;
wire [3:0] q_dup_reqs;
wire [3:0][NUM_REQS-1:0][29:0] q_req_addr;
wire [NUM_REQS-1:0] q_req_tmask;
wire [`TEX_FILTER_BITS-1:0] q_req_filter;
wire [REQ_INFOW-1:0] q_req_info;
wire [`TEX_STRIDE_BITS-1:0] q_req_stride;
wire [3:0][NUM_REQS-1:0][1:0] q_align_offs;
wire [3:0] q_dup_reqs;
assign reqq_push = req_valid && req_ready;
VX_fifo_queue #(
.DATAW ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFO_WIDTH + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * NUM_REQS * 2) + 4),
.DATAW ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFOW + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * NUM_REQS * 2) + 4),
.SIZE (`LSUQ_SIZE),
.OUTPUT_REG (1)
) req_queue (
@@ -244,7 +244,7 @@ module VX_tex_memory #(
assign reqq_pop = rsp_texels_done && ~stall_out;
VX_pipe_register #(
.DATAW (1 + NUM_REQS + REQ_INFO_WIDTH + (4 * NUM_REQS * 32)),
.DATAW (1 + NUM_REQS + REQ_INFOW + (4 * NUM_REQS * 32)),
.RESETW (1)
) rsp_pipe_reg (
.clk (clk),

16
hw/rtl/tex_unit/VX_tex_sampler.v
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@@ -1,9 +1,9 @@
`include "VX_tex_define.vh"
module VX_tex_sampler #(
parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1,
parameter NUM_REQS = 1
parameter CORE_ID = 0,
parameter REQ_INFOW = 1,
parameter NUM_REQS = 1
) (
input wire clk,
input wire reset,
@@ -14,14 +14,14 @@ module VX_tex_sampler #(
input wire [`TEX_FORMAT_BITS-1:0] req_format,
input wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] req_blends,
input wire [NUM_REQS-1:0][3:0][31:0] req_data,
input wire [REQ_INFO_WIDTH-1:0] req_info,
input wire [REQ_INFOW-1:0] req_info,
output wire req_ready,
// ouputs
output wire rsp_valid,
output wire [NUM_REQS-1:0] rsp_tmask,
output wire [NUM_REQS-1:0][31:0] rsp_data,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
output wire [REQ_INFOW-1:0] rsp_info,
input wire rsp_ready
);
@@ -29,7 +29,7 @@ module VX_tex_sampler #(
wire valid_s0;
wire [NUM_REQS-1:0] tmask_s0;
wire [REQ_INFO_WIDTH-1:0] req_info_s0;
wire [REQ_INFOW-1:0] req_info_s0;
wire [NUM_REQS-1:0][31:0] texel_ul, texel_uh;
wire [NUM_REQS-1:0][31:0] texel_ul_s0, texel_uh_s0;
wire [NUM_REQS-1:0][`BLEND_FRAC-1:0] blend_v, blend_v_s0;
@@ -76,7 +76,7 @@ module VX_tex_sampler #(
end
VX_pipe_register #(
.DATAW (1 + NUM_REQS + REQ_INFO_WIDTH + (NUM_REQS * `BLEND_FRAC) + (2 * NUM_REQS * 32)),
.DATAW (1 + NUM_REQS + REQ_INFOW + (NUM_REQS * `BLEND_FRAC) + (2 * NUM_REQS * 32)),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
@@ -103,7 +103,7 @@ module VX_tex_sampler #(
assign stall_out = rsp_valid && ~rsp_ready;
VX_pipe_register #(
.DATAW (1 + NUM_REQS + REQ_INFO_WIDTH + (NUM_REQS * 32)),
.DATAW (1 + NUM_REQS + REQ_INFOW + (NUM_REQS * 32)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),

30
hw/rtl/tex_unit/VX_tex_unit.v
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@@ -18,9 +18,9 @@ module VX_tex_unit #(
VX_tex_rsp_if tex_rsp_if
);
localparam REQ_INFO_WIDTH_S = `NR_BITS + 1 + `NW_BITS + 32;
localparam REQ_INFO_WIDTH_A = `TEX_FORMAT_BITS + REQ_INFO_WIDTH_S;
localparam REQ_INFO_WIDTH_M = (2 * `NUM_THREADS * `BLEND_FRAC) + REQ_INFO_WIDTH_A;
localparam REQ_INFOW_S = `NR_BITS + 1 + `NW_BITS + 32;
localparam REQ_INFOW_A = `TEX_FORMAT_BITS + REQ_INFOW_S;
localparam REQ_INFOW_M = (2 * `NUM_THREADS * `BLEND_FRAC) + REQ_INFOW_A;
reg [`TEX_MIPOFF_BITS-1:0] tex_mipoff [`NUM_TEX_UNITS-1:0][(1 << `TEX_LOD_BITS)-1:0];
reg [1:0][`TEX_DIM_BITS-1:0] tex_dims [`NUM_TEX_UNITS-1:0][(1 << `TEX_LOD_BITS)-1:0];
@@ -96,13 +96,13 @@ module VX_tex_unit #(
wire [`TEX_STRIDE_BITS-1:0] mem_req_stride;
wire [`NUM_THREADS-1:0][1:0][`BLEND_FRAC-1:0] mem_req_blends;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
wire [REQ_INFO_WIDTH_A-1:0] mem_req_info;
wire [REQ_INFOW_A-1:0] mem_req_info;
wire mem_req_ready;
VX_tex_addr #(
.CORE_ID (CORE_ID),
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A),
.NUM_REQS (`NUM_THREADS)
.CORE_ID (CORE_ID),
.REQ_INFOW (REQ_INFOW_A),
.NUM_REQS (`NUM_THREADS)
) tex_addr (
.clk (clk),
.reset (reset),
@@ -134,13 +134,13 @@ module VX_tex_unit #(
wire mem_rsp_valid;
wire [`NUM_THREADS-1:0] mem_rsp_tmask;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info;
wire [REQ_INFOW_M-1:0] mem_rsp_info;
wire mem_rsp_ready;
VX_tex_memory #(
.CORE_ID (CORE_ID),
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_M),
.NUM_REQS (`NUM_THREADS)
.CORE_ID (CORE_ID),
.REQ_INFOW (REQ_INFOW_M),
.NUM_REQS (`NUM_THREADS)
) tex_memory (
.clk (clk),
.reset (reset),
@@ -170,14 +170,14 @@ module VX_tex_unit #(
wire [`NUM_THREADS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends;
wire [`TEX_FORMAT_BITS-1:0] rsp_format;
wire [REQ_INFO_WIDTH_S-1:0] rsp_info;
wire [REQ_INFOW_S-1:0] rsp_info;
assign {rsp_blends, rsp_format, rsp_info} = mem_rsp_info;
VX_tex_sampler #(
.CORE_ID (CORE_ID),
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_S),
.NUM_REQS (`NUM_THREADS)
.CORE_ID (CORE_ID),
.REQ_INFOW (REQ_INFOW_S),
.NUM_REQS (`NUM_THREADS)
) tex_sampler (
.clk (clk),
.reset (reset),