From e795f7333e4f27bd0b527f2317a0e8fd952ab38a Mon Sep 17 00:00:00 2001
From: trmontgomery <tiffany.re.montgomery@gmail.com>
Date: Sat, 5 Sep 2020 17:11:26 -0400
Subject: [PATCH] separated tests

---
 hw/unit_tests/cache/cachesim.cpp  |   2 +
 hw/unit_tests/cache/cachesim.h    |   1 +
 hw/unit_tests/cache/testbench.cpp | 116 +++++++++++++++++++++++++++++-
 3 files changed, 117 insertions(+), 2 deletions(-)

diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp
index 7644cf7a..e4f6bfdb 100644
--- a/hw/unit_tests/cache/cachesim.cpp
+++ b/hw/unit_tests/cache/cachesim.cpp
@@ -254,12 +254,14 @@ void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
   rsp[1] = cache_->core_rsp_data[1];
   rsp[2] = cache_->core_rsp_data[2];
   rsp[3] = cache_->core_rsp_data[3];
+
   //std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
   //std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
   //std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
 }
 
 void CacheSim::get_core_req(){
+  std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
   char check = cache_->core_req_valid;
   std::cout << std::hex << "core_req_valid: " << check << std::endl;
   std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;
diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h
index bd40d0b6..84af025a 100644
--- a/hw/unit_tests/cache/cachesim.h
+++ b/hw/unit_tests/cache/cachesim.h
@@ -52,6 +52,7 @@ public:
   void clear_req(); 
   void send_req(core_req_t *req);
   bool assert_equal(unsigned int* data, unsigned int tag);
+  //void time_analyisis 
 
   //display funcs
 
diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp
index ef4f41b4..bf4cd602 100644
--- a/hw/unit_tests/cache/testbench.cpp
+++ b/hw/unit_tests/cache/testbench.cpp
@@ -6,7 +6,7 @@
 #define VCD_OUTPUT 1
 
 
-int REQ_RSP(CacheSim *sim){
+int REQ_RSP(CacheSim *sim){ //verified
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
@@ -43,6 +43,117 @@ int REQ_RSP(CacheSim *sim){
   return check;
 }
 
+int HIT_1(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0x11;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0x22;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int MISS_1(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+int FLUSH(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+
 int BACK_PRESSURE(CacheSim *sim){
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
@@ -83,13 +194,14 @@ int BACK_PRESSURE(CacheSim *sim){
   return check;
 }
 
+
 int main(int argc, char **argv)
 {
   //init
   RAM ram;
 	CacheSim cachesim;
   cachesim.attach_ram(&ram);
-  int check = REQ_RSP(&cachesim);
+  int check = HIT_1(&cachesim);
   if(check){
     std::cout << "PASSED" << std::endl;
   } else {