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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

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This commit is contained in:
Blaise Tine
2021-01-10 20:26:15 -08:00
parent 06945533cf
commit e770824d47
11 changed files with 122 additions and 130 deletions
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53
hw/rtl/libs/VX_dp_ram.v
View File

@@ -23,23 +23,18 @@ module VX_dp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
if (rden)
@@ -60,15 +55,13 @@ module VX_dp_ram #(
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
end
@@ -88,15 +81,13 @@ module VX_dp_ram #(
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
if (rden)
@@ -118,15 +109,13 @@ module VX_dp_ram #(
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
end
@@ -142,15 +131,13 @@ module VX_dp_ram #(
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
end

30
hw/rtl/libs/VX_pending_size.v
View File

@@ -1,35 +1,47 @@
`include "VX_platform.vh"
module VX_pending_size #(
parameter SIZE = 1
parameter SIZE = 1,
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
output wire full
output wire empty,
output wire full,
output wire [SIZEW-1:0] size
);
localparam ADDRW = $clog2(SIZE);
reg [ADDRW-1:0] size_r;
reg [ADDRW-1:0] used_r;
reg empty_r;
reg full_r;
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
full_r <= 0;
used_r <= 0;
empty_r <= 0;
full_r <= 0;
end else begin
assert(!push || !full);
if (push) begin
if (!pop && (used_r == ADDRW'(SIZE-1)))
full_r <= 1;
if (!pop) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
end else if (pop) begin
full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
end
size_r <= size_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
used_r <= used_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
end
end
assign full = full_r;
assign empty = empty_r;
assign full = full_r;
assign size = {full_r, used_r};
endmodule