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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

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This commit is contained in:
Blaise Tine
2021-01-10 20:26:15 -08:00
parent 06945533cf
commit e770824d47
11 changed files with 122 additions and 130 deletions
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9
hw/rtl/fp_cores/VX_fp_cvt.v
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@@ -121,8 +121,7 @@ module VX_fp_cvt #(
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 +INT_EXP_WIDTH + INT_MAN_WIDTH + LZC_RESULT_WIDTH + 1)),
.RESETW (1),
.DEPTH (1)
.RESETW (1)
) pipe_reg0 (
.clk (clk),
.reset (reset),
@@ -182,8 +181,7 @@ module VX_fp_cvt #(
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + 2*INT_EXP_WIDTH)),
.RESETW (1),
.DEPTH (1)
.RESETW (1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
@@ -310,8 +308,7 @@ module VX_fp_cvt #(
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + 32 + 1)),
.RESETW (1),
.DEPTH (1)
.RESETW (1)
) pipe_reg2 (
.clk (clk),
.reset (reset),