fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00
parent 06945533cf
commit e770824d47
11 changed files with 122 additions and 130 deletions
--- a/hw/rtl/cache/VX_data_store.v
+++ b/hw/rtl/cache/VX_data_store.v
@@ -48,13 +48,14 @@ module VX_data_store #(
    VX_dp_ram #(
        .DATAW(CACHE_LINE_SIZE * 8),
        .SIZE(`LINES_PER_BANK),
+        .BYTEENW(CACHE_LINE_SIZE),
        .RWCHECK(1)
    ) data (
        .clk(clk),
        .waddr(write_addr),                                
        .raddr(read_addr),                
        .wren(write_enable),  
-        .byteen(1'b1),
+        .byteen(byte_enable),
        .rden(1'b1),
        .din(write_data),
        .dout(read_data)