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Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension

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This commit is contained in:
Santosh Raghav Srivatsan
2021-12-06 18:55:13 -05:00
parent 30a0d34151
commit e6eda67d0c
21 changed files with 459 additions and 316 deletions
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74
sim/simX/decode.h
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@@ -13,49 +13,49 @@ class Decoder {
public:
Decoder(const ArchDef &);
std::shared_ptr<Instr> decode(HalfWord code, HalfWord PC);
std::shared_ptr<Instr> decode(Word code, Word PC);
private:
HalfWord inst_s_;
HalfWord opcode_s_;
HalfWord reg_s_;
HalfWord func2_s_;
HalfWord func3_s_;
HalfWord shift_opcode_;
HalfWord shift_rd_;
HalfWord shift_rs1_;
HalfWord shift_rs2_;
HalfWord shift_rs3_;
HalfWord shift_func2_;
HalfWord shift_func3_;
HalfWord shift_func7_;
HalfWord shift_j_u_immed_;
HalfWord shift_s_b_immed_;
HalfWord shift_i_immed_;
Word inst_s_;
Word opcode_s_;
Word reg_s_;
Word func2_s_;
Word func3_s_;
Word shift_opcode_;
Word shift_rd_;
Word shift_rs1_;
Word shift_rs2_;
Word shift_rs3_;
Word shift_func2_;
Word shift_func3_;
Word shift_func7_;
Word shift_j_u_immed_;
Word shift_s_b_immed_;
Word shift_i_immed_;
HalfWord reg_mask_;
HalfWord func2_mask_;
HalfWord func3_mask_;
HalfWord func6_mask_;
HalfWord func7_mask_;
HalfWord opcode_mask_;
HalfWord i_imm_mask_;
HalfWord s_imm_mask_;
HalfWord b_imm_mask_;
HalfWord u_imm_mask_;
HalfWord j_imm_mask_;
HalfWord v_imm_mask_;
Word reg_mask_;
Word func2_mask_;
Word func3_mask_;
Word func6_mask_;
Word func7_mask_;
Word opcode_mask_;
Word i_imm_mask_;
Word s_imm_mask_;
Word b_imm_mask_;
Word u_imm_mask_;
Word j_imm_mask_;
Word v_imm_mask_;
//Vector
HalfWord shift_vset_;
HalfWord shift_vset_immed_;
HalfWord shift_vmask_;
HalfWord shift_vmop_;
HalfWord shift_vnf_;
HalfWord shift_func6_;
HalfWord vmask_s_;
HalfWord mop_s_;
Word shift_vset_;
Word shift_vset_immed_;
Word shift_vmask_;
Word shift_vmop_;
Word shift_vnf_;
Word shift_func6_;
Word vmask_s_;
Word mop_s_;
};
}