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Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension

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This commit is contained in:
Santosh Raghav Srivatsan
2021-12-06 18:55:13 -05:00
parent 30a0d34151
commit e6eda67d0c
21 changed files with 459 additions and 316 deletions
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24
sim/simX/core.cpp
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@@ -241,7 +241,7 @@ void Core::writeback() {
inst_in_writeback_.next(NULL);
}
Word Core::get_csr(Addr addr, int tid, int wid) {
DoubleWord Core::get_csr(Addr addr, int tid, int wid) {
if (addr == CSR_FFLAGS) {
return fcsrs_.at(wid) & 0x1F;
} else if (addr == CSR_FRM) {
@@ -284,19 +284,19 @@ Word Core::get_csr(Addr addr, int tid, int wid) {
return insts_;
} else if (addr == CSR_MINSTRET_H) {
// NumInsts
return (Word)(insts_ >> 32);
return (DoubleWord)(insts_ >> 32);
} else if (addr == CSR_MCYCLE) {
// NumCycles
return (Word)steps_;
return (DoubleWord)steps_;
} else if (addr == CSR_MCYCLE_H) {
// NumCycles
return (Word)(steps_ >> 32);
return (DoubleWord)(steps_ >> 32);
} else {
return csrs_.at(addr);
}
}
void Core::set_csr(Addr addr, Word value, int /*tid*/, int wid) {
void Core::set_csr(Addr addr, DoubleWord value, int /*tid*/, int wid) {
if (addr == CSR_FFLAGS) {
fcsrs_.at(wid) = (fcsrs_.at(wid) & ~0x1F) | (value & 0x1F);
} else if (addr == CSR_FRM) {
@@ -322,16 +322,16 @@ void Core::barrier(int bar_id, int count, int warp_id) {
}
// simx64
HalfWord Core::icache_fetch(Addr addr) {
HalfWord data;
mem_.read(&data, addr, sizeof(HalfWord), 0);
Word Core::icache_fetch(Addr addr) {
Word data;
mem_.read(&data, addr, sizeof(Word), 0);
return data;
}
// simx64
Word Core::dcache_read(Addr addr, Size size) {
DoubleWord Core::dcache_read(Addr addr, Size size) {
++loads_;
Word data = 0;
DoubleWord data = 0;
#ifdef SM_ENABLE
if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 3) < SMEM_BASE_ADDR)) {
@@ -343,7 +343,7 @@ Word Core::dcache_read(Addr addr, Size size) {
return data;
}
void Core::dcache_write(Addr addr, Word data, Size size) {
void Core::dcache_write(Addr addr, DoubleWord data, Size size) {
++stores_;
#ifdef SM_ENABLE
if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE))
@@ -375,7 +375,7 @@ void Core::printStats() const {
<< "Stores: " << stores_ << std::endl;
}
void Core::writeToStdOut(Addr addr, Word data) {
void Core::writeToStdOut(Addr addr, DoubleWord data) {
uint32_t tid = (addr - IO_COUT_ADDR) & (IO_COUT_SIZE-1);
auto& ss_buf = print_bufs_[tid];
char c = (char)data;