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refactoring

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This commit is contained in:
Blaise Tine
2020-06-23 10:59:30 -07:00
parent 5e718c2676
commit e6cc221a44
21 changed files with 236 additions and 320 deletions
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22
hw/rtl/VX_gpr_wrapper.v
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@@ -2,13 +2,9 @@
module VX_gpr_wrapper (
input wire clk,
input wire reset,
VX_gpr_read_if gpr_read_if,
VX_wb_if writeback_if,
VX_gpr_jal_if gpr_jal_if,
output wire [`NUM_THREADS-1:0][31:0] a_reg_data,
output wire [`NUM_THREADS-1:0][31:0] b_reg_data
input wire reset,
VX_wb_if writeback_if,
VX_gpr_read_if gpr_read_if
);
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_a_reg_data;
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0][31:0] tmp_b_reg_data;
@@ -17,13 +13,13 @@ module VX_gpr_wrapper (
genvar i;
generate
for (i = 0; i < `NUM_THREADS; i++) begin : jal_data_assign
assign jal_data[i] = gpr_jal_if.curr_PC;
assign jal_data[i] = gpr_read_if.curr_PC;
end
endgenerate
`ifndef ASIC
assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (tmp_a_reg_data[gpr_read_if.warp_num]));
assign b_reg_data = (tmp_b_reg_data[gpr_read_if.warp_num]);
assign gpr_read_if.a_reg_data = gpr_read_if.is_jal ? jal_data : tmp_a_reg_data[gpr_read_if.warp_num];
assign gpr_read_if.b_reg_data = tmp_b_reg_data[gpr_read_if.warp_num];
`else
wire [`NW_BITS-1:0] old_warp_num;
@@ -39,15 +35,15 @@ module VX_gpr_wrapper (
.out (old_warp_num)
);
assign a_reg_data = (gpr_jal_if.is_jal ? jal_data : (tmp_a_reg_data[old_warp_num]));
assign b_reg_data = (tmp_b_reg_data[old_warp_num]);
assign gpr_read_if.a_reg_data = gpr_jal_if.is_jal ? jal_data : tmp_a_reg_data[old_warp_num];
assign gpr_read_if.b_reg_data = tmp_b_reg_data[old_warp_num];
`endif
generate
for (i = 0; i < `NUM_WARPS; i++) begin : warp_gprs
wire write_ce = (i == writeback_if.warp_num);
VX_gpr gpr(
VX_gpr_ram gpr_ram(
.clk (clk),
.reset (reset),
.write_ce (write_ce),