refactoring
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@@ -5,28 +5,28 @@ module VX_front_end #(
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) (
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`SCOPE_SIGNALS_ISTAGE_IO
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input wire clk,
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input wire reset,
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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input wire schedule_delay,
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VX_warp_ctl_if warp_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_cache_core_rsp_if icache_rsp_if,
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VX_cache_core_req_if icache_req_if,
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VX_cache_core_rsp_if icache_rsp_if,
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VX_cache_core_req_if icache_req_if,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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VX_frE_to_bckE_req_if bckE_req_if,
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output wire busy
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VX_backend_req_if bckE_req_if,
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output wire busy
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);
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VX_inst_meta_if fe_inst_meta_fi();
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VX_inst_meta_if fe_inst_meta_fi2();
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VX_inst_meta_if fe_inst_meta_id();
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VX_frE_to_bckE_req_if frE_to_bckE_req_if();
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VX_backend_req_if frE_to_bckE_req_if();
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VX_inst_meta_if fd_inst_meta_de();
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wire total_freeze = schedule_delay;
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