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New Warp Scheduler + VCD Enable

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This commit is contained in:
felsabbagh3
2019-09-15 00:12:41 -04:00
parent fb3bc60189
commit e67310acfb
66 changed files with 568 additions and 12973 deletions
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2
rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -20,7 +20,7 @@ module VX_d_e_reg (
wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_gpr_stall == `STALL);
VX_generic_register #(.N(490)) d_e_reg
VX_generic_register #(.N(489)) d_e_reg
(
.clk (clk),
.reset(reset),

10
rtl/pipe_regs/VX_e_m_reg.v
View File

@@ -27,14 +27,18 @@ module VX_e_m_reg (
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(464)) f_d_reg
wire temp_out_jal;
assign out_jal = temp_out_jal && VX_mem_req.valid[0];
VX_generic_register #(.N(463)) f_d_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, temp_out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
);
endmodule // VX_e_m_reg

2
rtl/pipe_regs/VX_f_d_reg.v
View File

@@ -17,7 +17,7 @@ module VX_f_d_reg (
VX_generic_register #(.N(72)) f_d_reg
VX_generic_register #(.N(71)) f_d_reg
(
.clk (clk),
.reset(reset),