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using 44-bit perf counters - aligned with DSP counters width

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Blaise Tine
2021-02-28 02:05:47 -08:00
parent 9fda618815
commit e64996946d
9 changed files with 111 additions and 107 deletions
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16
hw/rtl/interfaces/VX_perf_cache_if.v
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@@ -5,14 +5,14 @@
interface VX_perf_cache_if ();
wire [63:0] reads;
wire [63:0] writes;
wire [63:0] read_misses;
wire [63:0] write_misses;
wire [63:0] bank_stalls;
wire [63:0] mshr_stalls;
wire [63:0] pipe_stalls;
wire [63:0] crsp_stalls;
wire [43:0] reads;
wire [43:0] writes;
wire [43:0] read_misses;
wire [43:0] write_misses;
wire [43:0] bank_stalls;
wire [43:0] mshr_stalls;
wire [43:0] pipe_stalls;
wire [43:0] crsp_stalls;
endinterface