From e6466b887c1c70695ba5f87cae477e0cbb36e8fb Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 20 Oct 2020 08:45:21 -0700 Subject: [PATCH] minor update --- hw/opae/vortex_afu.qsf | 2 +- hw/rtl/cache/VX_tag_data_store.v | 2 +- hw/rtl/libs/VX_generic_queue.v | 4 ++-- hw/syn/quartus/project.tcl | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/opae/vortex_afu.qsf b/hw/opae/vortex_afu.qsf index f515b639..c24f3549 100644 --- a/hw/opae/vortex_afu.qsf +++ b/hw/opae/vortex_afu.qsf @@ -1,7 +1,7 @@ # Analysis & Synthesis Assignments set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG diff --git a/hw/rtl/cache/VX_tag_data_store.v b/hw/rtl/cache/VX_tag_data_store.v index a03c890b..db99943c 100644 --- a/hw/rtl/cache/VX_tag_data_store.v +++ b/hw/rtl/cache/VX_tag_data_store.v @@ -78,7 +78,7 @@ module VX_tag_data_store #( .SIZE(`BANK_LINE_COUNT), .BYTEENW(`BANK_LINE_WORDS * WORD_SIZE), .BUFFERED(0), - .RWCHECK(1) + .RWCHECK(0) ) dp_ram ( .clk(clk), .waddr(write_addr), diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 3c5c9a78..68db0d4d 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -3,7 +3,7 @@ module VX_generic_queue #( parameter DATAW = 1, parameter SIZE = 2, - parameter BUFFERED = 0, + parameter BUFFERED = 1, parameter ADDRW = $clog2(SIZE), parameter SIZEW = $clog2(SIZE+1) ) ( @@ -85,7 +85,7 @@ module VX_generic_queue #( .DATAW(DATAW), .SIZE(SIZE), .BUFFERED(0), - .RWCHECK(1) + .RWCHECK(0) ) dp_ram ( .clk(clk), .waddr(wr_ptr_a), diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index 26d41900..0e85bf48 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -33,7 +33,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON set_global_assignment -name VERILOG_MACRO QUARTUS set_global_assignment -name VERILOG_MACRO SYNTHESIS set_global_assignment -name VERILOG_MACRO NDEBUG