From 4a5f4fe64ee99ace586904b96133998fc2acca5a Mon Sep 17 00:00:00 2001 From: Malik Aki Burton Date: Sun, 21 Feb 2021 12:23:32 -0500 Subject: [PATCH 1/7] Created Flubber FPGA Startup .md file --- Flubber_FPGA_Startup_Guide.md | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Flubber_FPGA_Startup_Guide.md diff --git a/Flubber_FPGA_Startup_Guide.md b/Flubber_FPGA_Startup_Guide.md new file mode 100644 index 00000000..97607608 --- /dev/null +++ b/Flubber_FPGA_Startup_Guide.md @@ -0,0 +1,52 @@ +# Flubber FPGA Startup and Configuration Guide + +Flubber OPAE setup +------------------ + + $ source /opt/inteldevstack/init_env_user.sh + $ export OPAE_HOME=/opt/opae/1.1.2 + $ export PATH=$OPAE_HOME/bin:$PATH + $ export C_INCLUDE_PATH=$OPAE_HOME/include:$C_INCLUDE_PATH + $ export LIBRARY_PATH=$OPAE_HOME/lib:$LIBRARY_PATH + $ export LD_LIBRARY_PATH=$OPAE_HOME/lib:$LD_LIBRARY_PATH + $ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain + $ export PATH=:/opt/verilator/bin:$PATH + $ export VERILATOR_ROOT=/opt/verilator + + +Flubber OPAE build +------------------ + +The Flubber FPGA has to following configuration options: +- 1 core fpga (fpga-1c) +- 2 cores fpga (fpga-2c) +- 4 cores fpga (fpga-4c) +- 8 cores fpga (fpga-8c) +- 16 cores fpga (fpga-16c) + $ cd hw/syn/opae + $ make fpga-`# of cores`c + +A new folder *build_fpga_`# of cores`c* will be created and the build will start and the build will take ~30-45 min to complete. +You could check last 10 lines in build log for possible errors or build completion. + $ tail -n 10 ./build_fpga_`# of cores`c/build.log +Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs. + $ ps -u `username` +If the build fails and you need to restart it, clean up the build folder using the following command: + $ make clean-fpga-`# of cores`c +The following file should exist when the build is done: + $ ls -lsa ./build_fpga_`# of cores`c/vortex_afu.gbs + +Signing the bitstream +--------------------- + $ cd ./build_fpga_`# of cores`c/ + $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs + + +Programming the FPGA +-------------------- + $ fpgasupdate vortex_afu_unsigned_ssl.gbs + +FPGA sample test running OpenCL sgemm kernel +-------------------------------------------- +Run the following from the Vortex root directory + $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64" \ No newline at end of file From 89e8629542aea360ab4c8521cb5ad45c8a20a8d7 Mon Sep 17 00:00:00 2001 From: Malik Aki Burton Date: Tue, 23 Feb 2021 10:09:31 -0500 Subject: [PATCH 2/7] Added Build Progress and Build Script Config sections to the Flubber FPGA Startup guide --- Flubber_FPGA_Startup_Guide.md | 36 +++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/Flubber_FPGA_Startup_Guide.md b/Flubber_FPGA_Startup_Guide.md index 97607608..cc908010 100644 --- a/Flubber_FPGA_Startup_Guide.md +++ b/Flubber_FPGA_Startup_Guide.md @@ -25,28 +25,44 @@ The Flubber FPGA has to following configuration options: - 16 cores fpga (fpga-16c) $ cd hw/syn/opae $ make fpga-`# of cores`c +Example: `make fpga-4c` -A new folder *build_fpga_`# of cores`c* will be created and the build will start and the build will take ~30-45 min to complete. -You could check last 10 lines in build log for possible errors or build completion. +A new folder *build_fpga_`# of cores`c* will be created and the build will start and take ~30-45 min to complete. + +Flubber Config Build Progress +----------------------------- + +You could check the last 10 lines in the build log for possible errors until build completion. $ tail -n 10 ./build_fpga_`# of cores`c/build.log +Example: `tail -n 10 ./build_fpga_4c/build.log` + Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs. $ ps -u `username` + If the build fails and you need to restart it, clean up the build folder using the following command: $ make clean-fpga-`# of cores`c -The following file should exist when the build is done: +Example: `make clean-fpga-4c` + +The file `vortex_afu.gbs` should exist when the build is done: $ ls -lsa ./build_fpga_`# of cores`c/vortex_afu.gbs -Signing the bitstream ---------------------- +Signing the bitstream and Programming the FPGA +---------------------------------------------- + $ cd ./build_fpga_`# of cores`c/ $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs - - -Programming the FPGA --------------------- $ fpgasupdate vortex_afu_unsigned_ssl.gbs FPGA sample test running OpenCL sgemm kernel -------------------------------------------- + Run the following from the Vortex root directory - $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64" \ No newline at end of file + $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64" + +Build Script Configuration +-------------------------- + +Inside the ci folder there is a script called `blackbox.sh` which runs different tests on the Vortex processor with different configurations. Run: + $ ./ci/blackbox.sh --help +To see the different configuration options available. +The most important ones are `--driver`, which runs the Vortex test on either the fpga, rtlsim, vlsim, or simx simulators, and `--perf`, which enables the profiling counters for each core. \ No newline at end of file From 88d5cd4979302a72cfa2863e34ab93b393a665dd Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Mar 2021 16:08:21 -0500 Subject: [PATCH 3/7] adding pre-built runtime binary --- runtime/libvortexrt.a | Bin 0 -> 13130 bytes runtime/libvortexrt.dump | 1030 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 1030 insertions(+) create mode 100644 runtime/libvortexrt.a create mode 100644 runtime/libvortexrt.dump diff --git a/runtime/libvortexrt.a b/runtime/libvortexrt.a new file mode 100644 index 0000000000000000000000000000000000000000..5f27ad6381c5cc4826d0b31f97adb3665de1aaa8 GIT binary patch literal 13130 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+ 0: 00000513 li a0,0 + 4: 0005006b 0x5006b + +00000008 : + 8: fc002573 csrr a0,0xfc0 + c: 0005006b 0x5006b + 10: 00000197 auipc gp,0x0 + 14: 00018193 mv gp,gp + 18: 00000117 auipc sp,0x0 + 1c: 00010113 mv sp,sp + 20: 00000597 auipc a1,0x0 + 24: 00058593 mv a1,a1 + 28: cc102673 csrr a2,0xcc1 + 2c: 02c585b3 mul a1,a1,a2 + 30: 40b10133 sub sp,sp,a1 + 34: cc3026f3 csrr a3,0xcc3 + 38: 00068663 beqz a3,44 + 3c: 00000513 li a0,0 + 40: 0005006b 0x5006b + +00000044 : + 44: 00008067 ret + +Disassembly of section .data: + +00000000 <__dso_handle>: + 0: 0000 unimp + ... + +Disassembly of section .init: + +00000000 <_start>: + 0: 00000597 auipc a1,0x0 + 4: 00058593 mv a1,a1 + 8: fc102573 csrr a0,0xfc1 + c: 00b5106b 0xb5106b + 10: ff9ff0ef jal ra,8 <_start+0x8> + 14: 00100513 li a0,1 + 18: 0005006b 0x5006b + 1c: 00000517 auipc a0,0x0 + 20: 00050513 mv a0,a0 + 24: 00000617 auipc a2,0x0 + 28: 00060613 mv a2,a2 + 2c: 40a60633 sub a2,a2,a0 + 30: 00000593 li a1,0 + 34: 00000097 auipc ra,0x0 + 38: 000080e7 jalr ra # 34 <_start+0x34> + 3c: 00000517 auipc a0,0x0 + 40: 00050513 mv a0,a0 + 44: 00000097 auipc ra,0x0 + 48: 000080e7 jalr ra # 44 <_start+0x44> + 4c: 00000097 auipc ra,0x0 + 50: 000080e7 jalr ra # 4c <_start+0x4c> + 54: 00000097 auipc ra,0x0 + 58: 000080e7 jalr ra # 54 <_start+0x54> + 5c: 00000317 auipc t1,0x0 + 60: 00030067 jr t1 # 5c <_start+0x5c> + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2341 jal 580 + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> + c: 0019 c.nop 6 + e: 0000 unimp + 10: 7205 lui tp,0xfffe1 + 12: 3376 fld ft6,376(sp) + 14: 6932 flw fs2,12(sp) + 16: 7032 flw ft0,44(sp) + 18: 5f30 lw a2,120(a4) + 1a: 326d jal fffff9c4 + 1c: 3070 fld fa2,224(s0) + 1e: 665f 7032 0030 0x307032665f + +vx_print.S.o: file format elf32-littleriscv + + +Disassembly of section .text: + +00000000 : + 0: 00000297 auipc t0,0x0 + 4: 00028293 mv t0,t0 + 8: 0002a283 lw t0,0(t0) # 0 + c: cc202373 csrr t1,0xcc2 + 10: 01031313 slli t1,t1,0x10 + 14: 00a36333 or t1,t1,a0 + 18: 0062a023 sw t1,0(t0) + 1c: 00008067 ret + +Disassembly of section .data: + +00000000 : + 0: fffc fsw fa5,124(a5) + 2: ffff 0xffff + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2341 jal 580 + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> + c: 0019 c.nop 6 + e: 0000 unimp + 10: 7205 lui tp,0xfffe1 + 12: 3376 fld ft6,376(sp) + 14: 6932 flw fs2,12(sp) + 16: 7032 flw ft0,44(sp) + 18: 5f30 lw a2,120(a4) + 1a: 326d jal fffff9c4 + 1c: 3070 fld fa2,224(s0) + 1e: 665f 7032 0030 0x307032665f + +vx_print.c.o: file format elf32-littleriscv + + +Disassembly of section .text.vx_vprintf: + +00000000 : + 0: 22050063 beqz a0,220 <.L24> + 4: f5010113 addi sp,sp,-176 + 8: 0a812423 sw s0,168(sp) + c: 09312e23 sw s3,156(sp) + 10: 0a112623 sw ra,172(sp) + 14: 0a912223 sw s1,164(sp) + 18: 0b212023 sw s2,160(sp) + 1c: 09412c23 sw s4,152(sp) + 20: 09512a23 sw s5,148(sp) + 24: 09612823 sw s6,144(sp) + 28: 09712623 sw s7,140(sp) + 2c: 00050993 mv s3,a0 + 30: 00054503 lbu a0,0(a0) + 34: 00198413 addi s0,s3,1 + 38: 1e050063 beqz a0,218 <.L25> + 3c: 000034b7 lui s1,0x3 + 40: 00000ab7 lui s5,0x0 + 44: 00058a13 mv s4,a1 + 48: 02500913 li s2,37 + 4c: 80948493 addi s1,s1,-2039 # 2809 <.L24+0x25e9> + 50: 000a8a93 mv s5,s5 + +00000054 <.L23>: + 54: 05250663 beq a0,s2,a0 <.L38> + 58: 00000097 auipc ra,0x0 + 5c: 000080e7 jalr ra # 58 <.L23+0x4> + 60: 00044503 lbu a0,0(s0) + 64: 00140b13 addi s6,s0,1 + 68: 000b0413 mv s0,s6 + 6c: fe0514e3 bnez a0,54 <.L23> + +00000070 <.L40>: + 70: 41340533 sub a0,s0,s3 + +00000074 <.L1>: + 74: 0ac12083 lw ra,172(sp) + 78: 0a812403 lw s0,168(sp) + 7c: 0a412483 lw s1,164(sp) + 80: 0a012903 lw s2,160(sp) + 84: 09c12983 lw s3,156(sp) + 88: 09812a03 lw s4,152(sp) + 8c: 09412a83 lw s5,148(sp) + 90: 09012b03 lw s6,144(sp) + 94: 08c12b83 lw s7,140(sp) + 98: 0b010113 addi sp,sp,176 + 9c: 00008067 ret + +000000a0 <.L38>: + a0: 00040b13 mv s6,s0 + a4: 00d00613 li a2,13 + a8: 00100693 li a3,1 + +000000ac <.L6>: + ac: 000b4703 lbu a4,0(s6) + b0: 000b0513 mv a0,s6 + b4: 001b0b13 addi s6,s6,1 + b8: fe070793 addi a5,a4,-32 + bc: 0ff7f793 andi a5,a5,255 + c0: 00f66863 bltu a2,a5,d0 <.L5> + c4: 00f697b3 sll a5,a3,a5 + c8: 0097f7b3 and a5,a5,s1 + cc: fe0790e3 bnez a5,ac <.L6> + +000000d0 <.L5>: + d0: 02a00793 li a5,42 + d4: 00f70c63 beq a4,a5,ec <.L7> + d8: 00a00613 li a2,10 + dc: 04010593 addi a1,sp,64 + e0: 00000097 auipc ra,0x0 + e4: 000080e7 jalr ra # e0 <.L5+0x10> + e8: 04012b03 lw s6,64(sp) + +000000ec <.L7>: + ec: 000b4783 lbu a5,0(s6) + f0: 02e00713 li a4,46 + f4: 001b0513 addi a0,s6,1 + f8: 0ee78263 beq a5,a4,1dc <.L39> + +000000fc <.L8>: + fc: fb478793 addi a5,a5,-76 + 100: 0ff7f793 andi a5,a5,255 + 104: 02e00713 li a4,46 + 108: 02f76463 bltu a4,a5,130 <.L10> + 10c: 00279793 slli a5,a5,0x2 + 110: 015787b3 add a5,a5,s5 + 114: 0007a783 lw a5,0(a5) + 118: 00078067 jr a5 + +0000011c <.L14>: + 11c: 001b4703 lbu a4,1(s6) + 120: 06800793 li a5,104 + 124: 08f70e63 beq a4,a5,1c0 <.L16> + +00000128 <.L11>: + 128: 00050b13 mv s6,a0 + 12c: 00150513 addi a0,a0,1 + +00000130 <.L10>: + 130: 05210023 sb s2,64(sp) + 134: 40850533 sub a0,a0,s0 + 138: 08a05e63 blez a0,1d4 <.L26> + +0000013c <.L41>: + 13c: 00040793 mv a5,s0 + 140: 04110713 addi a4,sp,65 + 144: 00a40633 add a2,s0,a0 + +00000148 <.L18>: + 148: 0007c683 lbu a3,0(a5) + 14c: 00178793 addi a5,a5,1 + 150: 00170713 addi a4,a4,1 + 154: fed70fa3 sb a3,-1(a4) + 158: fec798e3 bne a5,a2,148 <.L18> + 15c: 00150513 addi a0,a0,1 + +00000160 <.L17>: + 160: 08010793 addi a5,sp,128 + 164: 00a787b3 add a5,a5,a0 + 168: 000a0693 mv a3,s4 + 16c: 04010613 addi a2,sp,64 + 170: 10000593 li a1,256 + 174: 00010513 mv a0,sp + 178: fc078023 sb zero,-64(a5) + 17c: 00000097 auipc ra,0x0 + 180: 000080e7 jalr ra # 17c <.L17+0x1c> + 184: 00010413 mv s0,sp + 188: 00a10bb3 add s7,sp,a0 + 18c: 00a05c63 blez a0,1a4 <.L22> + +00000190 <.L21>: + 190: 00044503 lbu a0,0(s0) + 194: 00140413 addi s0,s0,1 + 198: 00000097 auipc ra,0x0 + 19c: 000080e7 jalr ra # 198 <.L21+0x8> + 1a0: fe8b98e3 bne s7,s0,190 <.L21> + +000001a4 <.L22>: + 1a4: 001b4503 lbu a0,1(s6) + 1a8: 002b0413 addi s0,s6,2 + 1ac: ea0514e3 bnez a0,54 <.L23> + 1b0: ec1ff06f j 70 <.L40> + +000001b4 <.L13>: + 1b4: 001b4703 lbu a4,1(s6) + 1b8: 06c00793 li a5,108 + 1bc: f6f716e3 bne a4,a5,128 <.L11> + +000001c0 <.L16>: + 1c0: 003b0513 addi a0,s6,3 + 1c4: 05210023 sb s2,64(sp) + 1c8: 40850533 sub a0,a0,s0 + 1cc: 002b0b13 addi s6,s6,2 + 1d0: f6a046e3 bgtz a0,13c <.L41> + +000001d4 <.L26>: + 1d4: 00100513 li a0,1 + 1d8: f89ff06f j 160 <.L17> + +000001dc <.L39>: + 1dc: 001b4703 lbu a4,1(s6) + 1e0: 02a00793 li a5,42 + 1e4: 00f71a63 bne a4,a5,1f8 <.L9> + 1e8: 002b4783 lbu a5,2(s6) + 1ec: 003b0513 addi a0,s6,3 + 1f0: 002b0b13 addi s6,s6,2 + 1f4: f09ff06f j fc <.L8> + +000001f8 <.L9>: + 1f8: 00a00613 li a2,10 + 1fc: 04010593 addi a1,sp,64 + 200: 00000097 auipc ra,0x0 + 204: 000080e7 jalr ra # 200 <.L9+0x8> + 208: 04012b03 lw s6,64(sp) + 20c: 000b4783 lbu a5,0(s6) + 210: 001b0513 addi a0,s6,1 + 214: ee9ff06f j fc <.L8> + +00000218 <.L25>: + 218: 00100513 li a0,1 + 21c: e59ff06f j 74 <.L1> + +00000220 <.L24>: + 220: fff00513 li a0,-1 + 224: 00008067 ret + +Disassembly of section .rodata.vx_vprintf: + +00000000 <.L12>: + ... + +Disassembly of section .text.vx_printf: + +00000000 : + 0: fc010113 addi sp,sp,-64 + 4: 02410313 addi t1,sp,36 + 8: 02b12223 sw a1,36(sp) + c: 00030593 mv a1,t1 + 10: 00112e23 sw ra,28(sp) + 14: 02c12423 sw a2,40(sp) + 18: 02d12623 sw a3,44(sp) + 1c: 02e12823 sw a4,48(sp) + 20: 02f12a23 sw a5,52(sp) + 24: 03012c23 sw a6,56(sp) + 28: 03112e23 sw a7,60(sp) + 2c: 00612623 sw t1,12(sp) + 30: 00000097 auipc ra,0x0 + 34: 000080e7 jalr ra # 30 + 38: 01c12083 lw ra,28(sp) + 3c: 04010113 addi sp,sp,64 + 40: 00008067 ret + +Disassembly of section .text.vx_prints: + +00000000 : + 0: ff010113 addi sp,sp,-16 + 4: 00812423 sw s0,8(sp) + 8: 00112623 sw ra,12(sp) + c: 00050413 mv s0,a0 + 10: 00054503 lbu a0,0(a0) + 14: 00050e63 beqz a0,30 <.L44> + 18: 00140413 addi s0,s0,1 + +0000001c <.L46>: + 1c: 00140413 addi s0,s0,1 + 20: 00000097 auipc ra,0x0 + 24: 000080e7 jalr ra # 20 <.L46+0x4> + 28: fff44503 lbu a0,-1(s0) + 2c: fe0518e3 bnez a0,1c <.L46> + +00000030 <.L44>: + 30: 00c12083 lw ra,12(sp) + 34: 00812403 lw s0,8(sp) + 38: 01010113 addi sp,sp,16 + 3c: 00008067 ret + +Disassembly of section .text.vx_printx: + +00000000 : + 0: ff010113 addi sp,sp,-16 + 4: 00912223 sw s1,4(sp) + 8: 00112623 sw ra,12(sp) + c: 00812423 sw s0,8(sp) + 10: 01212023 sw s2,0(sp) + 14: 00f00793 li a5,15 + 18: 00050493 mv s1,a0 + 1c: 06a7f063 bgeu a5,a0,7c <.L63> + 20: 00000937 lui s2,0x0 + 24: 00000693 li a3,0 + 28: 02000413 li s0,32 + 2c: 00090913 mv s2,s2 + +00000030 <.L53>: + 30: ffc40413 addi s0,s0,-4 + 34: 0084d7b3 srl a5,s1,s0 + 38: 00f7f793 andi a5,a5,15 + 3c: 00f90733 add a4,s2,a5 + 40: 00079463 bnez a5,48 <.L55> + 44: 00068a63 beqz a3,58 <.L56> + +00000048 <.L55>: + 48: 00074503 lbu a0,0(a4) + 4c: 00000097 auipc ra,0x0 + 50: 000080e7 jalr ra # 4c <.L55+0x4> + 54: 00100693 li a3,1 + +00000058 <.L56>: + 58: fc041ce3 bnez s0,30 <.L53> + 5c: 00812403 lw s0,8(sp) + 60: 00c12083 lw ra,12(sp) + 64: 00412483 lw s1,4(sp) + 68: 00012903 lw s2,0(sp) + 6c: 00a00513 li a0,10 + 70: 01010113 addi sp,sp,16 + 74: 00000317 auipc t1,0x0 + 78: 00030067 jr t1 # 74 <.L56+0x1c> + +0000007c <.L63>: + 7c: 000007b7 lui a5,0x0 + 80: 00078793 mv a5,a5 + 84: 00a784b3 add s1,a5,a0 + 88: 0004c503 lbu a0,0(s1) + 8c: 00000097 auipc ra,0x0 + 90: 000080e7 jalr ra # 8c <.L63+0x10> + 94: 00812403 lw s0,8(sp) + 98: 00c12083 lw ra,12(sp) + 9c: 00412483 lw s1,4(sp) + a0: 00012903 lw s2,0(sp) + a4: 00a00513 li a0,10 + a8: 01010113 addi sp,sp,16 + ac: 00000317 auipc t1,0x0 + b0: 00030067 jr t1 # ac <.L63+0x30> + +Disassembly of section .text.vx_printv: + +00000000 : + 0: ff010113 addi sp,sp,-16 + 4: 00812423 sw s0,8(sp) + 8: 00912223 sw s1,4(sp) + c: 00112623 sw ra,12(sp) + 10: 01212023 sw s2,0(sp) + 14: 00050413 mv s0,a0 + 18: 00054503 lbu a0,0(a0) + 1c: 00058493 mv s1,a1 + 20: 00050e63 beqz a0,3c <.L66> + 24: 00140413 addi s0,s0,1 + +00000028 <.L67>: + 28: 00140413 addi s0,s0,1 + 2c: 00000097 auipc ra,0x0 + 30: 000080e7 jalr ra # 2c <.L67+0x4> + 34: fff44503 lbu a0,-1(s0) + 38: fe0518e3 bnez a0,28 <.L67> + +0000003c <.L66>: + 3c: 00f00793 li a5,15 + 40: 00000693 li a3,0 + 44: 02000413 li s0,32 + 48: 0497fc63 bgeu a5,s1,a0 <.L82> + 4c: 00000937 lui s2,0x0 + 50: 00090913 mv s2,s2 + +00000054 <.L68>: + 54: ffc40413 addi s0,s0,-4 + 58: 0084d7b3 srl a5,s1,s0 + 5c: 00f7f793 andi a5,a5,15 + 60: 00f90733 add a4,s2,a5 + 64: 00079463 bnez a5,6c <.L70> + 68: 00068a63 beqz a3,7c <.L71> + +0000006c <.L70>: + 6c: 00074503 lbu a0,0(a4) + 70: 00000097 auipc ra,0x0 + 74: 000080e7 jalr ra # 70 <.L70+0x4> + 78: 00100693 li a3,1 + +0000007c <.L71>: + 7c: fc041ce3 bnez s0,54 <.L68> + 80: 00812403 lw s0,8(sp) + 84: 00c12083 lw ra,12(sp) + 88: 00412483 lw s1,4(sp) + 8c: 00012903 lw s2,0(sp) + 90: 00a00513 li a0,10 + 94: 01010113 addi sp,sp,16 + 98: 00000317 auipc t1,0x0 + 9c: 00030067 jr t1 # 98 <.L71+0x1c> + +000000a0 <.L82>: + a0: 000007b7 lui a5,0x0 + a4: 00078793 mv a5,a5 + a8: 009784b3 add s1,a5,s1 + ac: 0004c503 lbu a0,0(s1) + b0: 00000097 auipc ra,0x0 + b4: 000080e7 jalr ra # b0 <.L82+0x10> + b8: 00812403 lw s0,8(sp) + bc: 00c12083 lw ra,12(sp) + c0: 00412483 lw s1,4(sp) + c4: 00012903 lw s2,0(sp) + c8: 00a00513 li a0,10 + cc: 01010113 addi sp,sp,16 + d0: 00000317 auipc t1,0x0 + d4: 00030067 jr t1 # d0 <.L82+0x30> + +Disassembly of section .rodata.hextoa: + +00000000 : + 0: 3130 fld fa2,96(a0) + 2: 3332 fld ft6,296(sp) + 4: 3534 fld fa3,104(a0) + 6: 3736 fld fa4,360(sp) + 8: 3938 fld fa4,112(a0) + a: 6261 lui tp,0x18 + c: 66656463 bltu a0,t1,674 <.L24+0x454> + ... + +Disassembly of section .comment: + +00000000 <.comment>: + 0: 4700 lw s0,8(a4) + 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm + 6: 4728 lw a0,72(a4) + 8: 554e lw a0,240(sp) + a: 2029 jal 14 + c: 2e39 jal 32a <.L24+0x10a> + e: 2e32 fld ft8,264(sp) + 10: 0030 addi a2,sp,8 + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2541 jal 680 <.L24+0x460> + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> + c: 0000001b 0x1b + 10: 1004 addi s1,sp,32 + 12: 7205 lui tp,0xfffe1 + 14: 3376 fld ft6,376(sp) + 16: 6932 flw fs2,12(sp) + 18: 7032 flw ft0,44(sp) + 1a: 5f30 lw a2,120(a4) + 1c: 326d jal fffff9c6 <.L24+0xfffff7a6> + 1e: 3070 fld fa2,224(s0) + 20: 665f 7032 0030 0x307032665f + +vx_spawn.c.o: file format elf32-littleriscv + + +Disassembly of section .text.spawn_tasks_callback: + +00000000 : + 0: fe010113 addi sp,sp,-32 + 4: 00112e23 sw ra,28(sp) + 8: 00812c23 sw s0,24(sp) + c: 00912a23 sw s1,20(sp) + 10: 01212823 sw s2,16(sp) + 14: 01312623 sw s3,12(sp) + 18: fc0027f3 csrr a5,0xfc0 + 1c: 0007806b 0x7806b + 20: cc5026f3 csrr a3,0xcc5 + 24: cc3029f3 csrr s3,0xcc3 + 28: cc002773 csrr a4,0xcc0 + 2c: fc002673 csrr a2,0xfc0 + 30: 000007b7 lui a5,0x0 + 34: 00269693 slli a3,a3,0x2 + 38: 00078793 mv a5,a5 + 3c: 00d787b3 add a5,a5,a3 + 40: 0007a483 lw s1,0(a5) # 0 + 44: 0104a403 lw s0,16(s1) + 48: 00c4a683 lw a3,12(s1) + 4c: 0089a933 slt s2,s3,s0 + 50: 00040793 mv a5,s0 + 54: 00d90933 add s2,s2,a3 + 58: 03368433 mul s0,a3,s3 + 5c: 00f9d463 bge s3,a5,64 <.L2> + 60: 00098793 mv a5,s3 + +00000064 <.L2>: + 64: 00f40433 add s0,s0,a5 + 68: 0084a683 lw a3,8(s1) + 6c: 02c40433 mul s0,s0,a2 + 70: 02e907b3 mul a5,s2,a4 + 74: 00d40433 add s0,s0,a3 + 78: 00f40433 add s0,s0,a5 + 7c: 00890933 add s2,s2,s0 + 80: 01245e63 bge s0,s2,9c <.L3> + +00000084 <.L4>: + 84: 0004a783 lw a5,0(s1) + 88: 0044a583 lw a1,4(s1) + 8c: 00040513 mv a0,s0 + 90: 00140413 addi s0,s0,1 + 94: 000780e7 jalr a5 + 98: fe8916e3 bne s2,s0,84 <.L4> + +0000009c <.L3>: + 9c: 0019b993 seqz s3,s3 + a0: 0009806b 0x9806b + a4: 01c12083 lw ra,28(sp) + a8: 01812403 lw s0,24(sp) + ac: 01412483 lw s1,20(sp) + b0: 01012903 lw s2,16(sp) + b4: 00c12983 lw s3,12(sp) + b8: 02010113 addi sp,sp,32 + bc: 00008067 ret + +Disassembly of section .text.spawn_kernel_callback: + +00000000 : + 0: fe010113 addi sp,sp,-32 + 4: 00112e23 sw ra,28(sp) + 8: 00812c23 sw s0,24(sp) + c: 00912a23 sw s1,20(sp) + 10: 01212823 sw s2,16(sp) + 14: 01312623 sw s3,12(sp) + 18: 01412423 sw s4,8(sp) + 1c: 01512223 sw s5,4(sp) + 20: fc0027f3 csrr a5,0xfc0 + 24: 0007806b 0x7806b + 28: cc5026f3 csrr a3,0xcc5 + 2c: cc302973 csrr s2,0xcc3 + 30: cc002773 csrr a4,0xcc0 + 34: fc002673 csrr a2,0xfc0 + 38: 000007b7 lui a5,0x0 + 3c: 00269693 slli a3,a3,0x2 + 40: 00078793 mv a5,a5 + 44: 00d787b3 add a5,a5,a3 + 48: 0007a403 lw s0,0(a5) # 0 + 4c: 01442483 lw s1,20(s0) + 50: 01042683 lw a3,16(s0) + 54: 00992ab3 slt s5,s2,s1 + 58: 00048793 mv a5,s1 + 5c: 00da8ab3 add s5,s5,a3 + 60: 032684b3 mul s1,a3,s2 + 64: 00f95463 bge s2,a5,6c <.L9> + 68: 00090793 mv a5,s2 + +0000006c <.L9>: + 6c: 00f484b3 add s1,s1,a5 + 70: 00042583 lw a1,0(s0) + 74: 00c42683 lw a3,12(s0) + 78: 0005a983 lw s3,0(a1) + 7c: 0045aa03 lw s4,4(a1) + 80: 02c484b3 mul s1,s1,a2 + 84: 02ea87b3 mul a5,s5,a4 + 88: 00d484b3 add s1,s1,a3 + 8c: 00f484b3 add s1,s1,a5 + 90: 009a8ab3 add s5,s5,s1 + 94: 03498a33 mul s4,s3,s4 + 98: 0754c063 blt s1,s5,f8 <.L15> + 9c: 0800006f j 11c <.L10> + +000000a0 <.L17>: + a0: 01a44703 lbu a4,26(s0) + a4: 01944683 lbu a3,25(s0) + a8: 40e4d733 sra a4,s1,a4 + ac: 034707b3 mul a5,a4,s4 + b0: 40f487b3 sub a5,s1,a5 + b4: 06068063 beqz a3,114 <.L13> + +000000b8 <.L18>: + b8: 01b44683 lbu a3,27(s0) + bc: 40d7d6b3 sra a3,a5,a3 + +000000c0 <.L14>: + c0: 033688b3 mul a7,a3,s3 + c4: 0145ae03 lw t3,20(a1) + c8: 0105a303 lw t1,16(a1) + cc: 00c5a603 lw a2,12(a1) + d0: 00442803 lw a6,4(s0) + d4: 00842503 lw a0,8(s0) + d8: 00148493 addi s1,s1,1 + dc: 01c70733 add a4,a4,t3 + e0: 006686b3 add a3,a3,t1 + e4: 411787b3 sub a5,a5,a7 + e8: 00c78633 add a2,a5,a2 + ec: 000800e7 jalr a6 + f0: 029a8663 beq s5,s1,11c <.L10> + f4: 00042583 lw a1,0(s0) + +000000f8 <.L15>: + f8: 01844783 lbu a5,24(s0) + fc: fa0792e3 bnez a5,a0 <.L17> + 100: 0344c733 div a4,s1,s4 + 104: 01944683 lbu a3,25(s0) + 108: 034707b3 mul a5,a4,s4 + 10c: 40f487b3 sub a5,s1,a5 + 110: fa0694e3 bnez a3,b8 <.L18> + +00000114 <.L13>: + 114: 0337c6b3 div a3,a5,s3 + 118: fa9ff06f j c0 <.L14> + +0000011c <.L10>: + 11c: 00193913 seqz s2,s2 + 120: 0009006b 0x9006b + 124: 01c12083 lw ra,28(sp) + 128: 01812403 lw s0,24(sp) + 12c: 01412483 lw s1,20(sp) + 130: 01012903 lw s2,16(sp) + 134: 00c12983 lw s3,12(sp) + 138: 00812a03 lw s4,8(sp) + 13c: 00412a83 lw s5,4(sp) + 140: 02010113 addi sp,sp,32 + 144: 00008067 ret + +Disassembly of section .text.spawn_remaining_tasks_callback: + +00000000 : + 0: ff010113 addi sp,sp,-16 + 4: 00112623 sw ra,12(sp) + 8: 0005006b 0x5006b + c: cc502773 csrr a4,0xcc5 + 10: cc202573 csrr a0,0xcc2 + 14: 000007b7 lui a5,0x0 + 18: 00271713 slli a4,a4,0x2 + 1c: 00078793 mv a5,a5 + 20: 00e787b3 add a5,a5,a4 + 24: 0007a783 lw a5,0(a5) # 0 + 28: 0087a683 lw a3,8(a5) + 2c: 0007a703 lw a4,0(a5) + 30: 0047a583 lw a1,4(a5) + 34: 00d50533 add a0,a0,a3 + 38: 000700e7 jalr a4 + 3c: 00100793 li a5,1 + 40: 0007806b 0x7806b + 44: 00c12083 lw ra,12(sp) + 48: 01010113 addi sp,sp,16 + 4c: 00008067 ret + +Disassembly of section .text.vx_spawn_tasks: + +00000000 : + 0: fc010113 addi sp,sp,-64 + 4: 02112e23 sw ra,60(sp) + 8: 02812c23 sw s0,56(sp) + c: 02912a23 sw s1,52(sp) + 10: 03212823 sw s2,48(sp) + 14: 03312623 sw s3,44(sp) + 18: fc2026f3 csrr a3,0xfc2 + 1c: fc102873 csrr a6,0xfc1 + 20: fc002473 csrr s0,0xfc0 + 24: cc5027f3 csrr a5,0xcc5 + 28: 01f00713 li a4,31 + 2c: 0cf74463 blt a4,a5,f4 <.L21> + 30: 030408b3 mul a7,s0,a6 + 34: 00100713 li a4,1 + 38: 00a8d463 bge a7,a0,40 <.L23> + 3c: 03154733 div a4,a0,a7 + +00000040 <.L23>: + 40: 0ce6c863 blt a3,a4,110 <.L39> + 44: 0ae7d863 bge a5,a4,f4 <.L21> + +00000048 <.L41>: + 48: fff68693 addi a3,a3,-1 + 4c: 02e54333 div t1,a0,a4 + 50: 00030893 mv a7,t1 + 54: 00f69663 bne a3,a5,60 <.L25> + 58: 02e56533 rem a0,a0,a4 + 5c: 006508b3 add a7,a0,t1 + +00000060 <.L25>: + 60: 0288c4b3 div s1,a7,s0 + 64: 0288e933 rem s2,a7,s0 + 68: 0b04ca63 blt s1,a6,11c <.L32> + 6c: 00100693 li a3,1 + 70: 0304c733 div a4,s1,a6 + 74: 00070663 beqz a4,80 <.L26> + 78: 00070693 mv a3,a4 + 7c: 0304e733 rem a4,s1,a6 + +00000080 <.L26>: + 80: 000009b7 lui s3,0x0 + 84: 00098993 mv s3,s3 + 88: 00e12e23 sw a4,28(sp) + 8c: 00c10713 addi a4,sp,12 + 90: 00b12623 sw a1,12(sp) + 94: 00c12823 sw a2,16(sp) + 98: 00d12c23 sw a3,24(sp) + 9c: 02f30333 mul t1,t1,a5 + a0: 00279793 slli a5,a5,0x2 + a4: 00f987b3 add a5,s3,a5 + a8: 00e7a023 sw a4,0(a5) + ac: 00612a23 sw t1,20(sp) + b0: 06904c63 bgtz s1,128 <.L40> + +000000b4 <.L27>: + b4: 04090063 beqz s2,f4 <.L21> + b8: 02848433 mul s0,s1,s0 + bc: 00812a23 sw s0,20(sp) + c0: 0009006b 0x9006b + c4: cc5027f3 csrr a5,0xcc5 + c8: cc202573 csrr a0,0xcc2 + cc: 00279793 slli a5,a5,0x2 + d0: 00f989b3 add s3,s3,a5 + d4: 0009a783 lw a5,0(s3) # 0 + d8: 0087a683 lw a3,8(a5) + dc: 0007a703 lw a4,0(a5) + e0: 0047a583 lw a1,4(a5) + e4: 00d50533 add a0,a0,a3 + e8: 000700e7 jalr a4 + ec: 00100793 li a5,1 + f0: 0007806b 0x7806b + +000000f4 <.L21>: + f4: 03c12083 lw ra,60(sp) + f8: 03812403 lw s0,56(sp) + fc: 03412483 lw s1,52(sp) + 100: 03012903 lw s2,48(sp) + 104: 02c12983 lw s3,44(sp) + 108: 04010113 addi sp,sp,64 + 10c: 00008067 ret + +00000110 <.L39>: + 110: 00068713 mv a4,a3 + 114: f2e7cae3 blt a5,a4,48 <.L41> + 118: fddff06f j f4 <.L21> + +0000011c <.L32>: + 11c: 00000713 li a4,0 + 120: 00100693 li a3,1 + 124: f5dff06f j 80 <.L26> + +00000128 <.L40>: + 128: 00048713 mv a4,s1 + 12c: 00985463 bge a6,s1,134 <.L28> + 130: 00080713 mv a4,a6 + +00000134 <.L28>: + 134: 000007b7 lui a5,0x0 + 138: 00078793 mv a5,a5 + 13c: 00f7106b 0xf7106b + 140: 00000097 auipc ra,0x0 + 144: 000080e7 jalr ra # 140 <.L28+0xc> + 148: f6dff06f j b4 <.L27> + +Disassembly of section .text.vx_spawn_kernel: + +00000000 : + 0: fc010113 addi sp,sp,-64 + 4: 02112e23 sw ra,60(sp) + 8: 02812c23 sw s0,56(sp) + c: 02912a23 sw s1,52(sp) + 10: 03212823 sw s2,48(sp) + 14: 03312623 sw s3,44(sp) + 18: fc2028f3 csrr a7,0xfc2 + 1c: fc102373 csrr t1,0xfc1 + 20: fc002473 csrr s0,0xfc0 + 24: cc5027f3 csrr a5,0xcc5 + 28: 01f00713 li a4,31 + 2c: 0ef74663 blt a4,a5,118 <.L42> + 30: 00052e03 lw t3,0(a0) + 34: 00452683 lw a3,4(a0) + 38: 00852803 lw a6,8(a0) + 3c: 02830eb3 mul t4,t1,s0 + 40: 00100713 li a4,1 + 44: 02de06b3 mul a3,t3,a3 + 48: 03068833 mul a6,a3,a6 + 4c: 010ed463 bge t4,a6,54 <.L44> + 50: 03d84733 div a4,a6,t4 + +00000054 <.L44>: + 54: 0ee8c063 blt a7,a4,134 <.L64> + 58: 0ce7d063 bge a5,a4,118 <.L42> + +0000005c <.L67>: + 5c: fff88893 addi a7,a7,-1 + 60: 02e84eb3 div t4,a6,a4 + 64: 000e8493 mv s1,t4 + 68: 00f89663 bne a7,a5,74 <.L46> + 6c: 02e86733 rem a4,a6,a4 + 70: 01d704b3 add s1,a4,t4 + +00000074 <.L46>: + 74: 0284c933 div s2,s1,s0 + 78: 0284e4b3 rem s1,s1,s0 + 7c: 0c694263 blt s2,t1,140 <.L57> + 80: 00100293 li t0,1 + 84: 02694833 div a6,s2,t1 + 88: 00080663 beqz a6,94 <.L47> + 8c: 00080293 mv t0,a6 + 90: 02696833 rem a6,s2,t1 + +00000094 <.L47>: + 94: d006f7d3 fcvt.s.w fa5,a3 + 98: fff68f93 addi t6,a3,-1 + 9c: fffe0f13 addi t5,t3,-1 + a0: 000009b7 lui s3,0x0 + a4: 00dff6b3 and a3,t6,a3 + a8: 00098993 mv s3,s3 + ac: 0016b693 seqz a3,a3 + b0: 00a12223 sw a0,4(sp) + b4: 00b12423 sw a1,8(sp) + b8: 00c12623 sw a2,12(sp) + bc: 00512a23 sw t0,20(sp) + c0: 01012c23 sw a6,24(sp) + c4: 00d10e23 sb a3,28(sp) + c8: 02fe8733 mul a4,t4,a5 + cc: e0078ed3 fmv.x.w t4,fa5 + d0: d00e77d3 fcvt.s.w fa5,t3 + d4: 00279793 slli a5,a5,0x2 + d8: 01cf7e33 and t3,t5,t3 + dc: e00788d3 fmv.x.w a7,fa5 + e0: 417ede93 srai t4,t4,0x17 + e4: 001e3e13 seqz t3,t3 + e8: 4178d893 srai a7,a7,0x17 + ec: f81e8e93 addi t4,t4,-127 + f0: f8188893 addi a7,a7,-127 + f4: 00f987b3 add a5,s3,a5 + f8: 00e12823 sw a4,16(sp) + fc: 00410713 addi a4,sp,4 + 100: 01c10ea3 sb t3,29(sp) + 104: 01d10f23 sb t4,30(sp) + 108: 01110fa3 sb a7,31(sp) + 10c: 00e7a023 sw a4,0(a5) # 0 + 110: 03204e63 bgtz s2,14c <.L65> + 114: 04049e63 bnez s1,170 <.L66> + +00000118 <.L42>: + 118: 03c12083 lw ra,60(sp) + 11c: 03812403 lw s0,56(sp) + 120: 03412483 lw s1,52(sp) + 124: 03012903 lw s2,48(sp) + 128: 02c12983 lw s3,44(sp) + 12c: 04010113 addi sp,sp,64 + 130: 00008067 ret + +00000134 <.L64>: + 134: 00088713 mv a4,a7 + 138: f2e7c2e3 blt a5,a4,5c <.L67> + 13c: fddff06f j 118 <.L42> + +00000140 <.L57>: + 140: 00000813 li a6,0 + 144: 00100293 li t0,1 + 148: f4dff06f j 94 <.L47> + +0000014c <.L65>: + 14c: 00090713 mv a4,s2 + 150: 01235463 bge t1,s2,158 <.L49> + 154: 00030713 mv a4,t1 + +00000158 <.L49>: + 158: 000007b7 lui a5,0x0 + 15c: 00078793 mv a5,a5 + 160: 00f7106b 0xf7106b + 164: 00000097 auipc ra,0x0 + 168: 000080e7 jalr ra # 164 <.L49+0xc> + 16c: fa0486e3 beqz s1,118 <.L42> + +00000170 <.L66>: + 170: 02890433 mul s0,s2,s0 + 174: 00812823 sw s0,16(sp) + 178: 0004806b 0x4806b + 17c: cc502773 csrr a4,0xcc5 + 180: cc2027f3 csrr a5,0xcc2 + 184: 00271713 slli a4,a4,0x2 + 188: 00e989b3 add s3,s3,a4 + 18c: 0009a503 lw a0,0(s3) # 0 + 190: 00052583 lw a1,0(a0) + 194: 00c52683 lw a3,12(a0) + 198: 01854703 lbu a4,24(a0) + 19c: 0005a803 lw a6,0(a1) + 1a0: 0045a603 lw a2,4(a1) + 1a4: 00d787b3 add a5,a5,a3 + 1a8: 02c80633 mul a2,a6,a2 + 1ac: 06070e63 beqz a4,228 <.L50> + 1b0: 01a54703 lbu a4,26(a0) + 1b4: 40e7d733 sra a4,a5,a4 + +000001b8 <.L51>: + 1b8: 01954683 lbu a3,25(a0) + 1bc: 02e60633 mul a2,a2,a4 + 1c0: 40c787b3 sub a5,a5,a2 + 1c4: 04068e63 beqz a3,220 <.L52> + 1c8: 01b54883 lbu a7,27(a0) + 1cc: 4117d8b3 sra a7,a5,a7 + +000001d0 <.L53>: + 1d0: 03180833 mul a6,a6,a7 + 1d4: 0145ae03 lw t3,20(a1) + 1d8: 0105a683 lw a3,16(a1) + 1dc: 00c5a603 lw a2,12(a1) + 1e0: 00452303 lw t1,4(a0) + 1e4: 00852503 lw a0,8(a0) + 1e8: 01c70733 add a4,a4,t3 + 1ec: 00d886b3 add a3,a7,a3 + 1f0: 410787b3 sub a5,a5,a6 + 1f4: 00c78633 add a2,a5,a2 + 1f8: 000300e7 jalr t1 + 1fc: 00100793 li a5,1 + 200: 0007806b 0x7806b + 204: 03c12083 lw ra,60(sp) + 208: 03812403 lw s0,56(sp) + 20c: 03412483 lw s1,52(sp) + 210: 03012903 lw s2,48(sp) + 214: 02c12983 lw s3,44(sp) + 218: 04010113 addi sp,sp,64 + 21c: 00008067 ret + +00000220 <.L52>: + 220: 0307c8b3 div a7,a5,a6 + 224: fadff06f j 1d0 <.L53> + +00000228 <.L50>: + 228: 02c7c733 div a4,a5,a2 + 22c: f8dff06f j 1b8 <.L51> + +Disassembly of section .comment: + +00000000 <.comment>: + 0: 4700 lw s0,8(a4) + 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm + 6: 4728 lw a0,72(a4) + 8: 554e lw a0,240(sp) + a: 2029 jal 14 + c: 2e39 jal 32a <.L50+0x102> + e: 2e32 fld ft8,264(sp) + 10: 0030 addi a2,sp,8 + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2541 jal 680 <.L50+0x458> + 2: 0000 unimp + 4: 7200 flw fs0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> + c: 0000001b 0x1b + 10: 1004 addi s1,sp,32 + 12: 7205 lui tp,0xfffe1 + 14: 3376 fld ft6,376(sp) + 16: 6932 flw fs2,12(sp) + 18: 7032 flw ft0,44(sp) + 1a: 5f30 lw a2,120(a4) + 1c: 326d jal fffff9c6 <.L50+0xfffff79e> + 1e: 3070 fld fa2,224(s0) + 20: 665f 7032 0030 0x307032665f From fdfc8e9605455d8ae7ef6fefd1c982eaa087cb77 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Mar 2021 16:20:36 -0500 Subject: [PATCH 4/7] fixed unsued parameters warnings --- driver/opae/vlsim/verilator.vlt | 3 ++- driver/opae/vlsim/vortex_afu_shim.sv | 2 +- driver/rtlsim/verilator.vlt | 3 ++- hw/rtl/VX_alu_unit.v | 5 +++- hw/rtl/VX_core.v | 12 ++++------ hw/rtl/VX_decode.v | 3 ++- hw/rtl/VX_fpu_unit.v | 2 ++ hw/rtl/VX_gpr_stage.v | 2 ++ hw/rtl/VX_gpu_unit.v | 2 ++ hw/rtl/VX_ibuffer.v | 3 +++ hw/rtl/VX_icache_stage.v | 2 ++ hw/rtl/VX_lsu_unit.v | 2 ++ hw/rtl/VX_mem_unit.v | 28 ++++++++++------------- hw/rtl/VX_pipeline.v | 12 ++++------ hw/rtl/VX_platform.vh | 4 ++++ hw/rtl/VX_warp_sched.v | 3 +++ hw/rtl/VX_writeback.v | 3 +++ hw/rtl/afu/vortex_afu.sv | 7 +++--- hw/rtl/afu/vortex_afu.vh | 4 ++++ hw/rtl/cache/VX_bank.v | 7 +++--- hw/rtl/cache/VX_cache.v | 6 ++--- hw/rtl/cache/VX_data_access.v | 4 ++++ hw/rtl/cache/VX_flush_ctrl.v | 4 +--- hw/rtl/cache/VX_miss_resrv.v | 6 ++--- hw/rtl/cache/VX_shared_mem.v | 2 ++ hw/rtl/cache/VX_tag_access.v | 3 +++ hw/rtl/interfaces/VX_dcache_core_req_if.v | 7 +++--- hw/rtl/interfaces/VX_dcache_core_rsp_if.v | 7 +++--- hw/rtl/interfaces/VX_icache_core_req_if.v | 5 ++-- hw/rtl/interfaces/VX_icache_core_rsp_if.v | 5 ++-- hw/rtl/libs/VX_dp_ram.v | 1 - hw/rtl/libs/VX_fixed_arbiter.v | 1 + hw/rtl/libs/VX_skid_buffer.v | 3 +-- hw/rtl/libs/VX_sp_ram.v | 1 - hw/simulate/verilator.vlt | 3 ++- 35 files changed, 94 insertions(+), 73 deletions(-) diff --git a/driver/opae/vlsim/verilator.vlt b/driver/opae/vlsim/verilator.vlt index cb799b65..c9388d65 100644 --- a/driver/opae/vlsim/verilator.vlt +++ b/driver/opae/vlsim/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/driver/opae/vlsim/vortex_afu_shim.sv b/driver/opae/vlsim/vortex_afu_shim.sv index cf5735e4..0bcabd03 100644 --- a/driver/opae/vlsim/vortex_afu_shim.sv +++ b/driver/opae/vlsim/vortex_afu_shim.sv @@ -1,5 +1,5 @@ -`include "vortex_afu.vh" `include "VX_define.vh" +`include "vortex_afu.vh" /* verilator lint_off IMPORTSTAR */ import ccip_if_pkg::*; import local_mem_cfg_pkg::*; diff --git a/driver/rtlsim/verilator.vlt b/driver/rtlsim/verilator.vlt index c0cd70d7..8358315b 100644 --- a/driver/rtlsim/verilator.vlt +++ b/driver/rtlsim/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 0cab28e2..9751bb48 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -12,7 +12,10 @@ module VX_alu_unit #( // Outputs VX_branch_ctl_if branch_ctl_if, VX_commit_if alu_commit_if -); +); + + `UNUSED_PARAM (CORE_ID) + reg [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] add_result; wire [`NUM_THREADS-1:0][32:0] sub_result; diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 47f23d59..b34b6788 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -73,27 +73,23 @@ module VX_core #( VX_dcache_core_req_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_req_if(); VX_dcache_core_rsp_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_rsp_if(); VX_icache_core_req_if #( .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_req_if(); VX_icache_core_rsp_if #( .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_rsp_if(); VX_pipeline #( diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 5e4419da..f68ec116 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -15,9 +15,10 @@ module VX_decode #( VX_wstall_if wstall_if, VX_join_if join_if ); + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) `UNUSED_VAR (reset) - + reg [`EX_BITS-1:0] ex_type; reg [`OP_BITS-1:0] op_type; reg [`MOD_BITS-1:0] op_mod; diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index 1795a489..3b6dd20e 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -17,6 +17,8 @@ module VX_fpu_unit #( input wire[`NUM_WARPS-1:0] csr_pending, output wire[`NUM_WARPS-1:0] pending ); + + `UNUSED_PARAM (CORE_ID) localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); wire ready_in; diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 98c07d7c..9367dd75 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -13,6 +13,8 @@ module VX_gpr_stage #( // outputs VX_gpr_rsp_if gpr_rsp_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) // ensure r0 never gets written, which can happen before the reset diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 0c3b1a52..9d0615bb 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -15,6 +15,8 @@ module VX_gpu_unit #( VX_warp_ctl_if warp_ctl_if, VX_commit_if gpu_commit_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) `UNUSED_VAR (reset) diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index b4cc2d93..a67c7221 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -13,6 +13,9 @@ module VX_ibuffer #( // outputs VX_decode_if ibuf_deq_if ); + + `UNUSED_PARAM (CORE_ID) + localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; localparam SIZE = 3; localparam ADDRW = $clog2(SIZE); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index f30e930a..75688a68 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -18,6 +18,8 @@ module VX_icache_stage #( // reponse VX_ifetch_rsp_if ifetch_rsp_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 2fa7e50a..01a5f00b 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -20,6 +20,8 @@ module VX_lsu_unit #( VX_commit_if st_commit_if ); + `UNUSED_PARAM (CORE_ID) + wire req_valid; wire [`NUM_THREADS-1:0] req_tmask; wire [`NUM_THREADS-1:0][31:0] req_addr; diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 94a30651..9e3b36d1 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -41,31 +41,27 @@ module VX_mem_unit # ( ) dcache_dram_rsp_if(), icache_dram_rsp_if(); VX_dcache_core_req_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) dcache_req_if(); VX_dcache_core_rsp_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) dcache_rsp_if(); VX_dcache_core_req_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) smem_req_if(); VX_dcache_core_rsp_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) smem_rsp_if(); VX_databus_arb databus_arb ( diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 32dd4e64..91305a4f 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -63,8 +63,7 @@ module VX_pipeline #( VX_dcache_core_req_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_req_if(); assign dcache_req_valid = dcache_core_req_if.valid; @@ -82,8 +81,7 @@ module VX_pipeline #( VX_dcache_core_rsp_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_rsp_if(); assign dcache_core_rsp_if.valid = dcache_rsp_valid; @@ -97,8 +95,7 @@ module VX_pipeline #( VX_icache_core_req_if #( .WORD_SIZE(4), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_req_if(); assign icache_req_valid = icache_core_req_if.valid; @@ -112,8 +109,7 @@ module VX_pipeline #( VX_icache_core_rsp_if #( .WORD_SIZE(4), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_rsp_if(); assign icache_core_rsp_if.valid = icache_rsp_valid; diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 39c605c7..5ec9c74a 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -33,6 +33,10 @@ /* verilator lint_on DECLFILENAME */ \ /* verilator lint_on IMPLICIT */ +`define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ + localparam __``x = x; \ + /* verilator lint_on UNUSED */ + `define UNUSED_VAR(x) always @(x) begin end `define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 5bc7baad..20946fbf 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -18,6 +18,9 @@ module VX_warp_sched #( output wire busy ); + + `UNUSED_PARAM (CORE_ID) + wire join_fall; wire [31:0] join_pc; wire [`NUM_THREADS-1:0] join_tm; diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 27cfb4a0..4dee992f 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -15,6 +15,9 @@ module VX_writeback #( // outputs VX_writeback_if writeback_if ); + + `UNUSED_PARAM (CORE_ID) + wire ld_valid = ld_commit_if.valid && ld_commit_if.wb; wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb; wire csr_valid = csr_commit_if.valid && csr_commit_if.wb; diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index b70541c1..f6c0dc12 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -1,5 +1,5 @@ +`include "VX_define.vh" `ifndef NOPAE -`include "platform_if.vh" import local_mem_cfg_pkg::*; `include "afu_json_info.vh" `else @@ -10,8 +10,6 @@ import local_mem_cfg_pkg::*; /* verilator lint_on IMPORTSTAR */ `endif -`include "VX_define.vh" - module vortex_afu #( parameter NUM_LOCAL_MEM_BANKS = 2 ) ( @@ -993,6 +991,9 @@ VX_scope #( .bus_write(cmd_scope_write) ); +`else + `UNUSED_PARAM (MMIO_SCOPE_READ) + `UNUSED_PARAM (MMIO_SCOPE_WRITE) `endif endmodule \ No newline at end of file diff --git a/hw/rtl/afu/vortex_afu.vh b/hw/rtl/afu/vortex_afu.vh index 564fd96c..691d488c 100644 --- a/hw/rtl/afu/vortex_afu.vh +++ b/hw/rtl/afu/vortex_afu.vh @@ -1,14 +1,18 @@ `ifndef __VORTEX_AFU__ `define __VORTEX_AFU__ +`IGNORE_WARNINGS_BEGIN `include "ccip_if_pkg.sv" +`IGNORE_WARNINGS_END `define PLATFORM_PROVIDES_LOCAL_MEMORY `define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26 `define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512 `define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4 +`IGNORE_WARNINGS_BEGIN `include "local_mem_cfg_pkg.sv" +`IGNORE_WARNINGS_END `define AFU_ACCEL_NAME "vortex_afu" `define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 8c889e29..7629b264 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -22,8 +22,6 @@ module VX_bank #( parameter CREQ_SIZE = 1, // Miss Reserv Queue Knob parameter MSHR_SIZE = 1, - // DRAM Response Queue Size - parameter DRSQ_SIZE = 1, // DRAM Request Queue Size parameter DREQ_SIZE = 1, @@ -92,6 +90,8 @@ module VX_bank #( input wire [`LINE_SELECT_BITS-1:0] flush_addr ); + `UNUSED_PARAM (CORE_TAG_ID_BITS) + `ifdef DBG_CACHE_REQ_INFO /* verilator lint_off UNUSED */ wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1; @@ -420,8 +420,7 @@ module VX_bank #( VX_miss_resrv #( .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), + .CACHE_ID (CACHE_ID), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), .NUM_BANKS (NUM_BANKS), .NUM_PORTS (NUM_PORTS), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 92a1dd39..63133664 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -163,10 +163,9 @@ module VX_cache #( /////////////////////////////////////////////////////////////////////////// VX_flush_ctrl #( - .CACHE_SIZE (CACHE_SIZE), + .CACHE_SIZE (CACHE_SIZE), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE) + .NUM_BANKS (NUM_BANKS) ) flush_ctrl ( .clk (clk), .reset (reset), @@ -294,7 +293,6 @@ module VX_cache #( .NUM_REQS (NUM_REQS), .CREQ_SIZE (CREQ_SIZE), .MSHR_SIZE (MSHR_SIZE), - .DRSQ_SIZE (DRSQ_SIZE), .DREQ_SIZE (DREQ_SIZE), .WRITE_ENABLE (WRITE_ENABLE), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 01d600a1..fbec1107 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -38,6 +38,10 @@ module VX_data_access #( input wire [CACHE_LINE_SIZE-1:0] byteen, input wire [`CACHE_LINE_WIDTH-1:0] wdata ); + + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_PARAM (WORD_SIZE) `UNUSED_VAR (reset) `UNUSED_VAR (readen) diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.v index 41926bcc..261197b6 100644 --- a/hw/rtl/cache/VX_flush_ctrl.v +++ b/hw/rtl/cache/VX_flush_ctrl.v @@ -6,9 +6,7 @@ module VX_flush_ctrl #( // Size of line inside a bank in bytes parameter CACHE_LINE_SIZE = 1, // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1 + parameter NUM_BANKS = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index fce9e38f..55755d61 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -19,9 +19,7 @@ module VX_miss_resrv #( parameter MSHR_SIZE = 1, parameter ALM_FULL = (MSHR_SIZE-1), // core request tag size - parameter CORE_TAG_WIDTH = 1, - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0 + parameter CORE_TAG_WIDTH = 1 ) ( input wire clk, input wire reset, @@ -58,6 +56,8 @@ module VX_miss_resrv #( // dequeue input wire dequeue ); + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) localparam ADDRW = $clog2(MSHR_SIZE); reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table; diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 1a768495..4d9eee57 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -49,6 +49,8 @@ module VX_shared_mem #( ); `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (CORE_TAG_ID_BITS) localparam CACHE_LINE_SIZE = WORD_SIZE; diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index a92f3d12..829f4006 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -31,6 +31,9 @@ module VX_tag_access #( input wire is_flush, output wire tag_match ); + + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) `UNUSED_VAR (reset) `UNUSED_VAR (lookup) diff --git a/hw/rtl/interfaces/VX_dcache_core_req_if.v b/hw/rtl/interfaces/VX_dcache_core_req_if.v index 35a5836e..6fd95087 100644 --- a/hw/rtl/interfaces/VX_dcache_core_req_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_req_if.v @@ -4,10 +4,9 @@ `include "../cache/VX_cache_config.vh" interface VX_dcache_core_req_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter NUM_REQS = 1, + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire [NUM_REQS-1:0] valid; diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v index 7f4c5203..6732e455 100644 --- a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v @@ -4,10 +4,9 @@ `include "../cache/VX_cache_config.vh" interface VX_dcache_core_rsp_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter NUM_REQS = 1, + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire [NUM_REQS-1:0] valid; diff --git a/hw/rtl/interfaces/VX_icache_core_req_if.v b/hw/rtl/interfaces/VX_icache_core_req_if.v index a683226a..2edb05d9 100644 --- a/hw/rtl/interfaces/VX_icache_core_req_if.v +++ b/hw/rtl/interfaces/VX_icache_core_req_if.v @@ -4,9 +4,8 @@ `include "../cache/VX_cache_config.vh" interface VX_icache_core_req_if #( - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire valid; diff --git a/hw/rtl/interfaces/VX_icache_core_rsp_if.v b/hw/rtl/interfaces/VX_icache_core_rsp_if.v index e78e1e0b..54ffa56d 100644 --- a/hw/rtl/interfaces/VX_icache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_icache_core_rsp_if.v @@ -4,9 +4,8 @@ `include "../cache/VX_cache_config.vh" interface VX_icache_core_rsp_if #( - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire valid; diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index ed151ba0..f03788ad 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -8,7 +8,6 @@ module VX_dp_ram #( parameter BUFFERED = 0, parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0, parameter INITZERO = 0 ) ( diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 5eb13654..6608b7f0 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -14,6 +14,7 @@ module VX_fixed_arbiter #( output wire grant_valid ); + `UNUSED_PARAM (LOCK_ENABLE) `UNUSED_VAR (clk) `UNUSED_VAR (reset) `UNUSED_VAR (enable) diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index c7266c6e..08377cfb 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -4,8 +4,7 @@ module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter BUFFERED = 0, - parameter FASTRAM = 1 + parameter BUFFERED = 0 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 7cbf7048..5ed011ec 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -8,7 +8,6 @@ module VX_sp_ram #( parameter BUFFERED = 0, parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0, parameter INITZERO = 0 ) ( diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt index 5598b43e..1d596ab3 100644 --- a/hw/simulate/verilator.vlt +++ b/hw/simulate/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" +lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file From 6b03fc9dac36a7219bbecb4dc4d945f15ee0226c Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Mar 2021 17:45:59 -0500 Subject: [PATCH 5/7] minor update --- driver/opae/Makefile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/driver/opae/Makefile b/driver/opae/Makefile index 4264c2c0..926d0abf 100644 --- a/driver/opae/Makefile +++ b/driver/opae/Makefile @@ -109,10 +109,7 @@ clean-asesim: clean-vlsim: $(MAKE) -C vlsim clean -clean: - clean-fpga - clean-asesim - clean-vlsim +clean: clean-fpga clean-asesim clean-vlsim ifneq ($(MAKECMDGOALS),clean) -include .depend From c9542d09d617c02f254a766eef85a0556da63c1b Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Mar 2021 20:35:49 -0500 Subject: [PATCH 6/7] fix build break --- driver/opae/vlsim/verilator.vlt | 2 +- driver/rtlsim/verilator.vlt | 2 +- hw/simulate/verilator.vlt | 2 +- runtime/Makefile | 22 +- runtime/libvortexrt.a | Bin 13130 -> 0 bytes runtime/libvortexrt.dump | 1030 ------------------------------- 6 files changed, 16 insertions(+), 1042 deletions(-) delete mode 100644 runtime/libvortexrt.a delete mode 100644 runtime/libvortexrt.dump diff --git a/driver/opae/vlsim/verilator.vlt b/driver/opae/vlsim/verilator.vlt index c9388d65..c7a98916 100644 --- a/driver/opae/vlsim/verilator.vlt +++ b/driver/opae/vlsim/verilator.vlt @@ -7,4 +7,4 @@ lint_off -rule UNUSED -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/driver/rtlsim/verilator.vlt b/driver/rtlsim/verilator.vlt index 8358315b..792578ea 100644 --- a/driver/rtlsim/verilator.vlt +++ b/driver/rtlsim/verilator.vlt @@ -7,4 +7,4 @@ lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt index 1d596ab3..dd69f119 100644 --- a/hw/simulate/verilator.vlt +++ b/hw/simulate/verilator.vlt @@ -7,4 +7,4 @@ lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" -lint_off -rule LATCH -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/runtime/Makefile b/runtime/Makefile index ba9d1366..b575f223 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -12,24 +12,28 @@ PROJECT = libvortexrt SRCS = ./src/vx_start.S ./src/vx_print.S ./src/vx_print.c ./src/vx_spawn.c -OBJS := $(addsuffix .o, $(notdir $(SRCS))) +OBJS := $(SRCS:.S=.o) $(SRCS:.c=.o) all: $(PROJECT).a $(PROJECT).dump +$(PROJECT).a: $(OBJS) + $(AR) rc $(PROJECT).a $^ + $(PROJECT).dump: $(PROJECT).a $(DP) -D $(PROJECT).a > $(PROJECT).dump -%.S.o: src/%.S - $(CC) $(CFLAGS) -c $< -o $@ +%.o: src/%.S + $(CC) $(CFLAGS) -c -o $@ $< -%.c.o: src/%.c - $(CC) $(CFLAGS) -c $< -o $@ - -$(PROJECT).a: $(OBJS) - $(AR) rc $(PROJECT).a $^ +%.o: src/%.c + $(CC) $(CFLAGS) -c -o $@ $< .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.a *.o *.dump .depend \ No newline at end of file + rm -rf *.a *.o *.dump .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif \ No newline at end of file diff --git a/runtime/libvortexrt.a b/runtime/libvortexrt.a deleted file mode 100644 index 5f27ad6381c5cc4826d0b31f97adb3665de1aaa8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13130 zcmdT~3vg7|dH(O-edtxO(qbe7brx0#@u(uPLO{%3%apZ!r)6$IH#j)FQr_jO1NtqUpNuZrJ#+4oHG}9785O!76?>qOL z)nN@bPMn$apE>t_|98&$&pH1+=iGDu-AVIPJ>L4ymV7#Xqck=*Cg;sbHa9fJ;|(gy zzQ*ITl1;k8ni3Hy7jf!uOhtb!Qu-esO!4a?qp3aJo9gM6t=rnuoxSbpZfWn_wxL(r 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00000597 auipc a1,0x0 - 24: 00058593 mv a1,a1 - 28: cc102673 csrr a2,0xcc1 - 2c: 02c585b3 mul a1,a1,a2 - 30: 40b10133 sub sp,sp,a1 - 34: cc3026f3 csrr a3,0xcc3 - 38: 00068663 beqz a3,44 - 3c: 00000513 li a0,0 - 40: 0005006b 0x5006b - -00000044 : - 44: 00008067 ret - -Disassembly of section .data: - -00000000 <__dso_handle>: - 0: 0000 unimp - ... - -Disassembly of section .init: - -00000000 <_start>: - 0: 00000597 auipc a1,0x0 - 4: 00058593 mv a1,a1 - 8: fc102573 csrr a0,0xfc1 - c: 00b5106b 0xb5106b - 10: ff9ff0ef jal ra,8 <_start+0x8> - 14: 00100513 li a0,1 - 18: 0005006b 0x5006b - 1c: 00000517 auipc a0,0x0 - 20: 00050513 mv a0,a0 - 24: 00000617 auipc a2,0x0 - 28: 00060613 mv a2,a2 - 2c: 40a60633 sub a2,a2,a0 - 30: 00000593 li a1,0 - 34: 00000097 auipc ra,0x0 - 38: 000080e7 jalr ra # 34 <_start+0x34> - 3c: 00000517 auipc a0,0x0 - 40: 00050513 mv a0,a0 - 44: 00000097 auipc ra,0x0 - 48: 000080e7 jalr ra # 44 <_start+0x44> - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <_start+0x4c> - 54: 00000097 auipc ra,0x0 - 58: 000080e7 jalr ra # 54 <_start+0x54> - 5c: 00000317 auipc t1,0x0 - 60: 00030067 jr t1 # 5c <_start+0x5c> - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 - 1c: 3070 fld fa2,224(s0) - 1e: 665f 7032 0030 0x307032665f - -vx_print.S.o: file format elf32-littleriscv - - -Disassembly of section .text: - -00000000 : - 0: 00000297 auipc t0,0x0 - 4: 00028293 mv t0,t0 - 8: 0002a283 lw t0,0(t0) # 0 - c: cc202373 csrr t1,0xcc2 - 10: 01031313 slli t1,t1,0x10 - 14: 00a36333 or t1,t1,a0 - 18: 0062a023 sw t1,0(t0) - 1c: 00008067 ret - -Disassembly of section .data: - -00000000 : - 0: fffc fsw fa5,124(a5) - 2: ffff 0xffff - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2341 jal 580 - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0019 c.nop 6 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3376 fld ft6,376(sp) - 14: 6932 flw fs2,12(sp) - 16: 7032 flw ft0,44(sp) - 18: 5f30 lw a2,120(a4) - 1a: 326d jal fffff9c4 - 1c: 3070 fld fa2,224(s0) - 1e: 665f 7032 0030 0x307032665f - -vx_print.c.o: file format elf32-littleriscv - - -Disassembly of section .text.vx_vprintf: - -00000000 : - 0: 22050063 beqz a0,220 <.L24> - 4: f5010113 addi sp,sp,-176 - 8: 0a812423 sw s0,168(sp) - c: 09312e23 sw s3,156(sp) - 10: 0a112623 sw ra,172(sp) - 14: 0a912223 sw s1,164(sp) - 18: 0b212023 sw s2,160(sp) - 1c: 09412c23 sw s4,152(sp) - 20: 09512a23 sw s5,148(sp) - 24: 09612823 sw s6,144(sp) - 28: 09712623 sw s7,140(sp) - 2c: 00050993 mv s3,a0 - 30: 00054503 lbu a0,0(a0) - 34: 00198413 addi s0,s3,1 - 38: 1e050063 beqz a0,218 <.L25> - 3c: 000034b7 lui s1,0x3 - 40: 00000ab7 lui s5,0x0 - 44: 00058a13 mv s4,a1 - 48: 02500913 li s2,37 - 4c: 80948493 addi s1,s1,-2039 # 2809 <.L24+0x25e9> - 50: 000a8a93 mv s5,s5 - -00000054 <.L23>: - 54: 05250663 beq a0,s2,a0 <.L38> - 58: 00000097 auipc ra,0x0 - 5c: 000080e7 jalr ra # 58 <.L23+0x4> - 60: 00044503 lbu a0,0(s0) - 64: 00140b13 addi s6,s0,1 - 68: 000b0413 mv s0,s6 - 6c: fe0514e3 bnez a0,54 <.L23> - -00000070 <.L40>: - 70: 41340533 sub a0,s0,s3 - -00000074 <.L1>: - 74: 0ac12083 lw ra,172(sp) - 78: 0a812403 lw s0,168(sp) - 7c: 0a412483 lw s1,164(sp) - 80: 0a012903 lw s2,160(sp) - 84: 09c12983 lw s3,156(sp) - 88: 09812a03 lw s4,152(sp) - 8c: 09412a83 lw s5,148(sp) - 90: 09012b03 lw s6,144(sp) - 94: 08c12b83 lw s7,140(sp) - 98: 0b010113 addi sp,sp,176 - 9c: 00008067 ret - -000000a0 <.L38>: - a0: 00040b13 mv s6,s0 - a4: 00d00613 li a2,13 - a8: 00100693 li a3,1 - -000000ac <.L6>: - ac: 000b4703 lbu a4,0(s6) - b0: 000b0513 mv a0,s6 - b4: 001b0b13 addi s6,s6,1 - b8: fe070793 addi a5,a4,-32 - bc: 0ff7f793 andi a5,a5,255 - c0: 00f66863 bltu a2,a5,d0 <.L5> - c4: 00f697b3 sll a5,a3,a5 - c8: 0097f7b3 and a5,a5,s1 - cc: fe0790e3 bnez a5,ac <.L6> - -000000d0 <.L5>: - d0: 02a00793 li a5,42 - d4: 00f70c63 beq a4,a5,ec <.L7> - d8: 00a00613 li a2,10 - dc: 04010593 addi a1,sp,64 - e0: 00000097 auipc ra,0x0 - e4: 000080e7 jalr ra # e0 <.L5+0x10> - e8: 04012b03 lw s6,64(sp) - -000000ec <.L7>: - ec: 000b4783 lbu a5,0(s6) - f0: 02e00713 li a4,46 - f4: 001b0513 addi a0,s6,1 - f8: 0ee78263 beq a5,a4,1dc <.L39> - -000000fc <.L8>: - fc: fb478793 addi a5,a5,-76 - 100: 0ff7f793 andi a5,a5,255 - 104: 02e00713 li a4,46 - 108: 02f76463 bltu a4,a5,130 <.L10> - 10c: 00279793 slli a5,a5,0x2 - 110: 015787b3 add a5,a5,s5 - 114: 0007a783 lw a5,0(a5) - 118: 00078067 jr a5 - -0000011c <.L14>: - 11c: 001b4703 lbu a4,1(s6) - 120: 06800793 li a5,104 - 124: 08f70e63 beq a4,a5,1c0 <.L16> - -00000128 <.L11>: - 128: 00050b13 mv s6,a0 - 12c: 00150513 addi a0,a0,1 - -00000130 <.L10>: - 130: 05210023 sb s2,64(sp) - 134: 40850533 sub a0,a0,s0 - 138: 08a05e63 blez a0,1d4 <.L26> - -0000013c <.L41>: - 13c: 00040793 mv a5,s0 - 140: 04110713 addi a4,sp,65 - 144: 00a40633 add a2,s0,a0 - -00000148 <.L18>: - 148: 0007c683 lbu a3,0(a5) - 14c: 00178793 addi a5,a5,1 - 150: 00170713 addi a4,a4,1 - 154: fed70fa3 sb a3,-1(a4) - 158: fec798e3 bne a5,a2,148 <.L18> - 15c: 00150513 addi a0,a0,1 - -00000160 <.L17>: - 160: 08010793 addi a5,sp,128 - 164: 00a787b3 add a5,a5,a0 - 168: 000a0693 mv a3,s4 - 16c: 04010613 addi a2,sp,64 - 170: 10000593 li a1,256 - 174: 00010513 mv a0,sp - 178: fc078023 sb zero,-64(a5) - 17c: 00000097 auipc ra,0x0 - 180: 000080e7 jalr ra # 17c <.L17+0x1c> - 184: 00010413 mv s0,sp - 188: 00a10bb3 add s7,sp,a0 - 18c: 00a05c63 blez a0,1a4 <.L22> - -00000190 <.L21>: - 190: 00044503 lbu a0,0(s0) - 194: 00140413 addi s0,s0,1 - 198: 00000097 auipc ra,0x0 - 19c: 000080e7 jalr ra # 198 <.L21+0x8> - 1a0: fe8b98e3 bne s7,s0,190 <.L21> - -000001a4 <.L22>: - 1a4: 001b4503 lbu a0,1(s6) - 1a8: 002b0413 addi s0,s6,2 - 1ac: ea0514e3 bnez a0,54 <.L23> - 1b0: ec1ff06f j 70 <.L40> - -000001b4 <.L13>: - 1b4: 001b4703 lbu a4,1(s6) - 1b8: 06c00793 li a5,108 - 1bc: f6f716e3 bne a4,a5,128 <.L11> - -000001c0 <.L16>: - 1c0: 003b0513 addi a0,s6,3 - 1c4: 05210023 sb s2,64(sp) - 1c8: 40850533 sub a0,a0,s0 - 1cc: 002b0b13 addi s6,s6,2 - 1d0: f6a046e3 bgtz a0,13c <.L41> - -000001d4 <.L26>: - 1d4: 00100513 li a0,1 - 1d8: f89ff06f j 160 <.L17> - -000001dc <.L39>: - 1dc: 001b4703 lbu a4,1(s6) - 1e0: 02a00793 li a5,42 - 1e4: 00f71a63 bne a4,a5,1f8 <.L9> - 1e8: 002b4783 lbu a5,2(s6) - 1ec: 003b0513 addi a0,s6,3 - 1f0: 002b0b13 addi s6,s6,2 - 1f4: f09ff06f j fc <.L8> - -000001f8 <.L9>: - 1f8: 00a00613 li a2,10 - 1fc: 04010593 addi a1,sp,64 - 200: 00000097 auipc ra,0x0 - 204: 000080e7 jalr ra # 200 <.L9+0x8> - 208: 04012b03 lw s6,64(sp) - 20c: 000b4783 lbu a5,0(s6) - 210: 001b0513 addi a0,s6,1 - 214: ee9ff06f j fc <.L8> - -00000218 <.L25>: - 218: 00100513 li a0,1 - 21c: e59ff06f j 74 <.L1> - -00000220 <.L24>: - 220: fff00513 li a0,-1 - 224: 00008067 ret - -Disassembly of section .rodata.vx_vprintf: - -00000000 <.L12>: - ... - -Disassembly of section .text.vx_printf: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02410313 addi t1,sp,36 - 8: 02b12223 sw a1,36(sp) - c: 00030593 mv a1,t1 - 10: 00112e23 sw ra,28(sp) - 14: 02c12423 sw a2,40(sp) - 18: 02d12623 sw a3,44(sp) - 1c: 02e12823 sw a4,48(sp) - 20: 02f12a23 sw a5,52(sp) - 24: 03012c23 sw a6,56(sp) - 28: 03112e23 sw a7,60(sp) - 2c: 00612623 sw t1,12(sp) - 30: 00000097 auipc ra,0x0 - 34: 000080e7 jalr ra # 30 - 38: 01c12083 lw ra,28(sp) - 3c: 04010113 addi sp,sp,64 - 40: 00008067 ret - -Disassembly of section .text.vx_prints: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00812423 sw s0,8(sp) - 8: 00112623 sw ra,12(sp) - c: 00050413 mv s0,a0 - 10: 00054503 lbu a0,0(a0) - 14: 00050e63 beqz a0,30 <.L44> - 18: 00140413 addi s0,s0,1 - -0000001c <.L46>: - 1c: 00140413 addi s0,s0,1 - 20: 00000097 auipc ra,0x0 - 24: 000080e7 jalr ra # 20 <.L46+0x4> - 28: fff44503 lbu a0,-1(s0) - 2c: fe0518e3 bnez a0,1c <.L46> - -00000030 <.L44>: - 30: 00c12083 lw ra,12(sp) - 34: 00812403 lw s0,8(sp) - 38: 01010113 addi sp,sp,16 - 3c: 00008067 ret - -Disassembly of section .text.vx_printx: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00912223 sw s1,4(sp) - 8: 00112623 sw ra,12(sp) - c: 00812423 sw s0,8(sp) - 10: 01212023 sw s2,0(sp) - 14: 00f00793 li a5,15 - 18: 00050493 mv s1,a0 - 1c: 06a7f063 bgeu a5,a0,7c <.L63> - 20: 00000937 lui s2,0x0 - 24: 00000693 li a3,0 - 28: 02000413 li s0,32 - 2c: 00090913 mv s2,s2 - -00000030 <.L53>: - 30: ffc40413 addi s0,s0,-4 - 34: 0084d7b3 srl a5,s1,s0 - 38: 00f7f793 andi a5,a5,15 - 3c: 00f90733 add a4,s2,a5 - 40: 00079463 bnez a5,48 <.L55> - 44: 00068a63 beqz a3,58 <.L56> - -00000048 <.L55>: - 48: 00074503 lbu a0,0(a4) - 4c: 00000097 auipc ra,0x0 - 50: 000080e7 jalr ra # 4c <.L55+0x4> - 54: 00100693 li a3,1 - -00000058 <.L56>: - 58: fc041ce3 bnez s0,30 <.L53> - 5c: 00812403 lw s0,8(sp) - 60: 00c12083 lw ra,12(sp) - 64: 00412483 lw s1,4(sp) - 68: 00012903 lw s2,0(sp) - 6c: 00a00513 li a0,10 - 70: 01010113 addi sp,sp,16 - 74: 00000317 auipc t1,0x0 - 78: 00030067 jr t1 # 74 <.L56+0x1c> - -0000007c <.L63>: - 7c: 000007b7 lui a5,0x0 - 80: 00078793 mv a5,a5 - 84: 00a784b3 add s1,a5,a0 - 88: 0004c503 lbu a0,0(s1) - 8c: 00000097 auipc ra,0x0 - 90: 000080e7 jalr ra # 8c <.L63+0x10> - 94: 00812403 lw s0,8(sp) - 98: 00c12083 lw ra,12(sp) - 9c: 00412483 lw s1,4(sp) - a0: 00012903 lw s2,0(sp) - a4: 00a00513 li a0,10 - a8: 01010113 addi sp,sp,16 - ac: 00000317 auipc t1,0x0 - b0: 00030067 jr t1 # ac <.L63+0x30> - -Disassembly of section .text.vx_printv: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00812423 sw s0,8(sp) - 8: 00912223 sw s1,4(sp) - c: 00112623 sw ra,12(sp) - 10: 01212023 sw s2,0(sp) - 14: 00050413 mv s0,a0 - 18: 00054503 lbu a0,0(a0) - 1c: 00058493 mv s1,a1 - 20: 00050e63 beqz a0,3c <.L66> - 24: 00140413 addi s0,s0,1 - -00000028 <.L67>: - 28: 00140413 addi s0,s0,1 - 2c: 00000097 auipc ra,0x0 - 30: 000080e7 jalr ra # 2c <.L67+0x4> - 34: fff44503 lbu a0,-1(s0) - 38: fe0518e3 bnez a0,28 <.L67> - -0000003c <.L66>: - 3c: 00f00793 li a5,15 - 40: 00000693 li a3,0 - 44: 02000413 li s0,32 - 48: 0497fc63 bgeu a5,s1,a0 <.L82> - 4c: 00000937 lui s2,0x0 - 50: 00090913 mv s2,s2 - -00000054 <.L68>: - 54: ffc40413 addi s0,s0,-4 - 58: 0084d7b3 srl a5,s1,s0 - 5c: 00f7f793 andi a5,a5,15 - 60: 00f90733 add a4,s2,a5 - 64: 00079463 bnez a5,6c <.L70> - 68: 00068a63 beqz a3,7c <.L71> - -0000006c <.L70>: - 6c: 00074503 lbu a0,0(a4) - 70: 00000097 auipc ra,0x0 - 74: 000080e7 jalr ra # 70 <.L70+0x4> - 78: 00100693 li a3,1 - -0000007c <.L71>: - 7c: fc041ce3 bnez s0,54 <.L68> - 80: 00812403 lw s0,8(sp) - 84: 00c12083 lw ra,12(sp) - 88: 00412483 lw s1,4(sp) - 8c: 00012903 lw s2,0(sp) - 90: 00a00513 li a0,10 - 94: 01010113 addi sp,sp,16 - 98: 00000317 auipc t1,0x0 - 9c: 00030067 jr t1 # 98 <.L71+0x1c> - -000000a0 <.L82>: - a0: 000007b7 lui a5,0x0 - a4: 00078793 mv a5,a5 - a8: 009784b3 add s1,a5,s1 - ac: 0004c503 lbu a0,0(s1) - b0: 00000097 auipc ra,0x0 - b4: 000080e7 jalr ra # b0 <.L82+0x10> - b8: 00812403 lw s0,8(sp) - bc: 00c12083 lw ra,12(sp) - c0: 00412483 lw s1,4(sp) - c4: 00012903 lw s2,0(sp) - c8: 00a00513 li a0,10 - cc: 01010113 addi sp,sp,16 - d0: 00000317 auipc t1,0x0 - d4: 00030067 jr t1 # d0 <.L82+0x30> - -Disassembly of section .rodata.hextoa: - -00000000 : - 0: 3130 fld fa2,96(a0) - 2: 3332 fld ft6,296(sp) - 4: 3534 fld fa3,104(a0) - 6: 3736 fld fa4,360(sp) - 8: 3938 fld fa4,112(a0) - a: 6261 lui tp,0x18 - c: 66656463 bltu a0,t1,674 <.L24+0x454> - ... - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 4700 lw s0,8(a4) - 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm - 6: 4728 lw a0,72(a4) - 8: 554e lw a0,240(sp) - a: 2029 jal 14 - c: 2e39 jal 32a <.L24+0x10a> - e: 2e32 fld ft8,264(sp) - 10: 0030 addi a2,sp,8 - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2541 jal 680 <.L24+0x460> - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0000001b 0x1b - 10: 1004 addi s1,sp,32 - 12: 7205 lui tp,0xfffe1 - 14: 3376 fld ft6,376(sp) - 16: 6932 flw fs2,12(sp) - 18: 7032 flw ft0,44(sp) - 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <.L24+0xfffff7a6> - 1e: 3070 fld fa2,224(s0) - 20: 665f 7032 0030 0x307032665f - -vx_spawn.c.o: file format elf32-littleriscv - - -Disassembly of section .text.spawn_tasks_callback: - -00000000 : - 0: fe010113 addi sp,sp,-32 - 4: 00112e23 sw ra,28(sp) - 8: 00812c23 sw s0,24(sp) - c: 00912a23 sw s1,20(sp) - 10: 01212823 sw s2,16(sp) - 14: 01312623 sw s3,12(sp) - 18: fc0027f3 csrr a5,0xfc0 - 1c: 0007806b 0x7806b - 20: cc5026f3 csrr a3,0xcc5 - 24: cc3029f3 csrr s3,0xcc3 - 28: cc002773 csrr a4,0xcc0 - 2c: fc002673 csrr a2,0xfc0 - 30: 000007b7 lui a5,0x0 - 34: 00269693 slli a3,a3,0x2 - 38: 00078793 mv a5,a5 - 3c: 00d787b3 add a5,a5,a3 - 40: 0007a483 lw s1,0(a5) # 0 - 44: 0104a403 lw s0,16(s1) - 48: 00c4a683 lw a3,12(s1) - 4c: 0089a933 slt s2,s3,s0 - 50: 00040793 mv a5,s0 - 54: 00d90933 add s2,s2,a3 - 58: 03368433 mul s0,a3,s3 - 5c: 00f9d463 bge s3,a5,64 <.L2> - 60: 00098793 mv a5,s3 - -00000064 <.L2>: - 64: 00f40433 add s0,s0,a5 - 68: 0084a683 lw a3,8(s1) - 6c: 02c40433 mul s0,s0,a2 - 70: 02e907b3 mul a5,s2,a4 - 74: 00d40433 add s0,s0,a3 - 78: 00f40433 add s0,s0,a5 - 7c: 00890933 add s2,s2,s0 - 80: 01245e63 bge s0,s2,9c <.L3> - -00000084 <.L4>: - 84: 0004a783 lw a5,0(s1) - 88: 0044a583 lw a1,4(s1) - 8c: 00040513 mv a0,s0 - 90: 00140413 addi s0,s0,1 - 94: 000780e7 jalr a5 - 98: fe8916e3 bne s2,s0,84 <.L4> - -0000009c <.L3>: - 9c: 0019b993 seqz s3,s3 - a0: 0009806b 0x9806b - a4: 01c12083 lw ra,28(sp) - a8: 01812403 lw s0,24(sp) - ac: 01412483 lw s1,20(sp) - b0: 01012903 lw s2,16(sp) - b4: 00c12983 lw s3,12(sp) - b8: 02010113 addi sp,sp,32 - bc: 00008067 ret - -Disassembly of section .text.spawn_kernel_callback: - -00000000 : - 0: fe010113 addi sp,sp,-32 - 4: 00112e23 sw ra,28(sp) - 8: 00812c23 sw s0,24(sp) - c: 00912a23 sw s1,20(sp) - 10: 01212823 sw s2,16(sp) - 14: 01312623 sw s3,12(sp) - 18: 01412423 sw s4,8(sp) - 1c: 01512223 sw s5,4(sp) - 20: fc0027f3 csrr a5,0xfc0 - 24: 0007806b 0x7806b - 28: cc5026f3 csrr a3,0xcc5 - 2c: cc302973 csrr s2,0xcc3 - 30: cc002773 csrr a4,0xcc0 - 34: fc002673 csrr a2,0xfc0 - 38: 000007b7 lui a5,0x0 - 3c: 00269693 slli a3,a3,0x2 - 40: 00078793 mv a5,a5 - 44: 00d787b3 add a5,a5,a3 - 48: 0007a403 lw s0,0(a5) # 0 - 4c: 01442483 lw s1,20(s0) - 50: 01042683 lw a3,16(s0) - 54: 00992ab3 slt s5,s2,s1 - 58: 00048793 mv a5,s1 - 5c: 00da8ab3 add s5,s5,a3 - 60: 032684b3 mul s1,a3,s2 - 64: 00f95463 bge s2,a5,6c <.L9> - 68: 00090793 mv a5,s2 - -0000006c <.L9>: - 6c: 00f484b3 add s1,s1,a5 - 70: 00042583 lw a1,0(s0) - 74: 00c42683 lw a3,12(s0) - 78: 0005a983 lw s3,0(a1) - 7c: 0045aa03 lw s4,4(a1) - 80: 02c484b3 mul s1,s1,a2 - 84: 02ea87b3 mul a5,s5,a4 - 88: 00d484b3 add s1,s1,a3 - 8c: 00f484b3 add s1,s1,a5 - 90: 009a8ab3 add s5,s5,s1 - 94: 03498a33 mul s4,s3,s4 - 98: 0754c063 blt s1,s5,f8 <.L15> - 9c: 0800006f j 11c <.L10> - -000000a0 <.L17>: - a0: 01a44703 lbu a4,26(s0) - a4: 01944683 lbu a3,25(s0) - a8: 40e4d733 sra a4,s1,a4 - ac: 034707b3 mul a5,a4,s4 - b0: 40f487b3 sub a5,s1,a5 - b4: 06068063 beqz a3,114 <.L13> - -000000b8 <.L18>: - b8: 01b44683 lbu a3,27(s0) - bc: 40d7d6b3 sra a3,a5,a3 - -000000c0 <.L14>: - c0: 033688b3 mul a7,a3,s3 - c4: 0145ae03 lw t3,20(a1) - c8: 0105a303 lw t1,16(a1) - cc: 00c5a603 lw a2,12(a1) - d0: 00442803 lw a6,4(s0) - d4: 00842503 lw a0,8(s0) - d8: 00148493 addi s1,s1,1 - dc: 01c70733 add a4,a4,t3 - e0: 006686b3 add a3,a3,t1 - e4: 411787b3 sub a5,a5,a7 - e8: 00c78633 add a2,a5,a2 - ec: 000800e7 jalr a6 - f0: 029a8663 beq s5,s1,11c <.L10> - f4: 00042583 lw a1,0(s0) - -000000f8 <.L15>: - f8: 01844783 lbu a5,24(s0) - fc: fa0792e3 bnez a5,a0 <.L17> - 100: 0344c733 div a4,s1,s4 - 104: 01944683 lbu a3,25(s0) - 108: 034707b3 mul a5,a4,s4 - 10c: 40f487b3 sub a5,s1,a5 - 110: fa0694e3 bnez a3,b8 <.L18> - -00000114 <.L13>: - 114: 0337c6b3 div a3,a5,s3 - 118: fa9ff06f j c0 <.L14> - -0000011c <.L10>: - 11c: 00193913 seqz s2,s2 - 120: 0009006b 0x9006b - 124: 01c12083 lw ra,28(sp) - 128: 01812403 lw s0,24(sp) - 12c: 01412483 lw s1,20(sp) - 130: 01012903 lw s2,16(sp) - 134: 00c12983 lw s3,12(sp) - 138: 00812a03 lw s4,8(sp) - 13c: 00412a83 lw s5,4(sp) - 140: 02010113 addi sp,sp,32 - 144: 00008067 ret - -Disassembly of section .text.spawn_remaining_tasks_callback: - -00000000 : - 0: ff010113 addi sp,sp,-16 - 4: 00112623 sw ra,12(sp) - 8: 0005006b 0x5006b - c: cc502773 csrr a4,0xcc5 - 10: cc202573 csrr a0,0xcc2 - 14: 000007b7 lui a5,0x0 - 18: 00271713 slli a4,a4,0x2 - 1c: 00078793 mv a5,a5 - 20: 00e787b3 add a5,a5,a4 - 24: 0007a783 lw a5,0(a5) # 0 - 28: 0087a683 lw a3,8(a5) - 2c: 0007a703 lw a4,0(a5) - 30: 0047a583 lw a1,4(a5) - 34: 00d50533 add a0,a0,a3 - 38: 000700e7 jalr a4 - 3c: 00100793 li a5,1 - 40: 0007806b 0x7806b - 44: 00c12083 lw ra,12(sp) - 48: 01010113 addi sp,sp,16 - 4c: 00008067 ret - -Disassembly of section .text.vx_spawn_tasks: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02112e23 sw ra,60(sp) - 8: 02812c23 sw s0,56(sp) - c: 02912a23 sw s1,52(sp) - 10: 03212823 sw s2,48(sp) - 14: 03312623 sw s3,44(sp) - 18: fc2026f3 csrr a3,0xfc2 - 1c: fc102873 csrr a6,0xfc1 - 20: fc002473 csrr s0,0xfc0 - 24: cc5027f3 csrr a5,0xcc5 - 28: 01f00713 li a4,31 - 2c: 0cf74463 blt a4,a5,f4 <.L21> - 30: 030408b3 mul a7,s0,a6 - 34: 00100713 li a4,1 - 38: 00a8d463 bge a7,a0,40 <.L23> - 3c: 03154733 div a4,a0,a7 - -00000040 <.L23>: - 40: 0ce6c863 blt a3,a4,110 <.L39> - 44: 0ae7d863 bge a5,a4,f4 <.L21> - -00000048 <.L41>: - 48: fff68693 addi a3,a3,-1 - 4c: 02e54333 div t1,a0,a4 - 50: 00030893 mv a7,t1 - 54: 00f69663 bne a3,a5,60 <.L25> - 58: 02e56533 rem a0,a0,a4 - 5c: 006508b3 add a7,a0,t1 - -00000060 <.L25>: - 60: 0288c4b3 div s1,a7,s0 - 64: 0288e933 rem s2,a7,s0 - 68: 0b04ca63 blt s1,a6,11c <.L32> - 6c: 00100693 li a3,1 - 70: 0304c733 div a4,s1,a6 - 74: 00070663 beqz a4,80 <.L26> - 78: 00070693 mv a3,a4 - 7c: 0304e733 rem a4,s1,a6 - -00000080 <.L26>: - 80: 000009b7 lui s3,0x0 - 84: 00098993 mv s3,s3 - 88: 00e12e23 sw a4,28(sp) - 8c: 00c10713 addi a4,sp,12 - 90: 00b12623 sw a1,12(sp) - 94: 00c12823 sw a2,16(sp) - 98: 00d12c23 sw a3,24(sp) - 9c: 02f30333 mul t1,t1,a5 - a0: 00279793 slli a5,a5,0x2 - a4: 00f987b3 add a5,s3,a5 - a8: 00e7a023 sw a4,0(a5) - ac: 00612a23 sw t1,20(sp) - b0: 06904c63 bgtz s1,128 <.L40> - -000000b4 <.L27>: - b4: 04090063 beqz s2,f4 <.L21> - b8: 02848433 mul s0,s1,s0 - bc: 00812a23 sw s0,20(sp) - c0: 0009006b 0x9006b - c4: cc5027f3 csrr a5,0xcc5 - c8: cc202573 csrr a0,0xcc2 - cc: 00279793 slli a5,a5,0x2 - d0: 00f989b3 add s3,s3,a5 - d4: 0009a783 lw a5,0(s3) # 0 - d8: 0087a683 lw a3,8(a5) - dc: 0007a703 lw a4,0(a5) - e0: 0047a583 lw a1,4(a5) - e4: 00d50533 add a0,a0,a3 - e8: 000700e7 jalr a4 - ec: 00100793 li a5,1 - f0: 0007806b 0x7806b - -000000f4 <.L21>: - f4: 03c12083 lw ra,60(sp) - f8: 03812403 lw s0,56(sp) - fc: 03412483 lw s1,52(sp) - 100: 03012903 lw s2,48(sp) - 104: 02c12983 lw s3,44(sp) - 108: 04010113 addi sp,sp,64 - 10c: 00008067 ret - -00000110 <.L39>: - 110: 00068713 mv a4,a3 - 114: f2e7cae3 blt a5,a4,48 <.L41> - 118: fddff06f j f4 <.L21> - -0000011c <.L32>: - 11c: 00000713 li a4,0 - 120: 00100693 li a3,1 - 124: f5dff06f j 80 <.L26> - -00000128 <.L40>: - 128: 00048713 mv a4,s1 - 12c: 00985463 bge a6,s1,134 <.L28> - 130: 00080713 mv a4,a6 - -00000134 <.L28>: - 134: 000007b7 lui a5,0x0 - 138: 00078793 mv a5,a5 - 13c: 00f7106b 0xf7106b - 140: 00000097 auipc ra,0x0 - 144: 000080e7 jalr ra # 140 <.L28+0xc> - 148: f6dff06f j b4 <.L27> - -Disassembly of section .text.vx_spawn_kernel: - -00000000 : - 0: fc010113 addi sp,sp,-64 - 4: 02112e23 sw ra,60(sp) - 8: 02812c23 sw s0,56(sp) - c: 02912a23 sw s1,52(sp) - 10: 03212823 sw s2,48(sp) - 14: 03312623 sw s3,44(sp) - 18: fc2028f3 csrr a7,0xfc2 - 1c: fc102373 csrr t1,0xfc1 - 20: fc002473 csrr s0,0xfc0 - 24: cc5027f3 csrr a5,0xcc5 - 28: 01f00713 li a4,31 - 2c: 0ef74663 blt a4,a5,118 <.L42> - 30: 00052e03 lw t3,0(a0) - 34: 00452683 lw a3,4(a0) - 38: 00852803 lw a6,8(a0) - 3c: 02830eb3 mul t4,t1,s0 - 40: 00100713 li a4,1 - 44: 02de06b3 mul a3,t3,a3 - 48: 03068833 mul a6,a3,a6 - 4c: 010ed463 bge t4,a6,54 <.L44> - 50: 03d84733 div a4,a6,t4 - -00000054 <.L44>: - 54: 0ee8c063 blt a7,a4,134 <.L64> - 58: 0ce7d063 bge a5,a4,118 <.L42> - -0000005c <.L67>: - 5c: fff88893 addi a7,a7,-1 - 60: 02e84eb3 div t4,a6,a4 - 64: 000e8493 mv s1,t4 - 68: 00f89663 bne a7,a5,74 <.L46> - 6c: 02e86733 rem a4,a6,a4 - 70: 01d704b3 add s1,a4,t4 - -00000074 <.L46>: - 74: 0284c933 div s2,s1,s0 - 78: 0284e4b3 rem s1,s1,s0 - 7c: 0c694263 blt s2,t1,140 <.L57> - 80: 00100293 li t0,1 - 84: 02694833 div a6,s2,t1 - 88: 00080663 beqz a6,94 <.L47> - 8c: 00080293 mv t0,a6 - 90: 02696833 rem a6,s2,t1 - -00000094 <.L47>: - 94: d006f7d3 fcvt.s.w fa5,a3 - 98: fff68f93 addi t6,a3,-1 - 9c: fffe0f13 addi t5,t3,-1 - a0: 000009b7 lui s3,0x0 - a4: 00dff6b3 and a3,t6,a3 - a8: 00098993 mv s3,s3 - ac: 0016b693 seqz a3,a3 - b0: 00a12223 sw a0,4(sp) - b4: 00b12423 sw a1,8(sp) - b8: 00c12623 sw a2,12(sp) - bc: 00512a23 sw t0,20(sp) - c0: 01012c23 sw a6,24(sp) - c4: 00d10e23 sb a3,28(sp) - c8: 02fe8733 mul a4,t4,a5 - cc: e0078ed3 fmv.x.w t4,fa5 - d0: d00e77d3 fcvt.s.w fa5,t3 - d4: 00279793 slli a5,a5,0x2 - d8: 01cf7e33 and t3,t5,t3 - dc: e00788d3 fmv.x.w a7,fa5 - e0: 417ede93 srai t4,t4,0x17 - e4: 001e3e13 seqz t3,t3 - e8: 4178d893 srai a7,a7,0x17 - ec: f81e8e93 addi t4,t4,-127 - f0: f8188893 addi a7,a7,-127 - f4: 00f987b3 add a5,s3,a5 - f8: 00e12823 sw a4,16(sp) - fc: 00410713 addi a4,sp,4 - 100: 01c10ea3 sb t3,29(sp) - 104: 01d10f23 sb t4,30(sp) - 108: 01110fa3 sb a7,31(sp) - 10c: 00e7a023 sw a4,0(a5) # 0 - 110: 03204e63 bgtz s2,14c <.L65> - 114: 04049e63 bnez s1,170 <.L66> - -00000118 <.L42>: - 118: 03c12083 lw ra,60(sp) - 11c: 03812403 lw s0,56(sp) - 120: 03412483 lw s1,52(sp) - 124: 03012903 lw s2,48(sp) - 128: 02c12983 lw s3,44(sp) - 12c: 04010113 addi sp,sp,64 - 130: 00008067 ret - -00000134 <.L64>: - 134: 00088713 mv a4,a7 - 138: f2e7c2e3 blt a5,a4,5c <.L67> - 13c: fddff06f j 118 <.L42> - -00000140 <.L57>: - 140: 00000813 li a6,0 - 144: 00100293 li t0,1 - 148: f4dff06f j 94 <.L47> - -0000014c <.L65>: - 14c: 00090713 mv a4,s2 - 150: 01235463 bge t1,s2,158 <.L49> - 154: 00030713 mv a4,t1 - -00000158 <.L49>: - 158: 000007b7 lui a5,0x0 - 15c: 00078793 mv a5,a5 - 160: 00f7106b 0xf7106b - 164: 00000097 auipc ra,0x0 - 168: 000080e7 jalr ra # 164 <.L49+0xc> - 16c: fa0486e3 beqz s1,118 <.L42> - -00000170 <.L66>: - 170: 02890433 mul s0,s2,s0 - 174: 00812823 sw s0,16(sp) - 178: 0004806b 0x4806b - 17c: cc502773 csrr a4,0xcc5 - 180: cc2027f3 csrr a5,0xcc2 - 184: 00271713 slli a4,a4,0x2 - 188: 00e989b3 add s3,s3,a4 - 18c: 0009a503 lw a0,0(s3) # 0 - 190: 00052583 lw a1,0(a0) - 194: 00c52683 lw a3,12(a0) - 198: 01854703 lbu a4,24(a0) - 19c: 0005a803 lw a6,0(a1) - 1a0: 0045a603 lw a2,4(a1) - 1a4: 00d787b3 add a5,a5,a3 - 1a8: 02c80633 mul a2,a6,a2 - 1ac: 06070e63 beqz a4,228 <.L50> - 1b0: 01a54703 lbu a4,26(a0) - 1b4: 40e7d733 sra a4,a5,a4 - -000001b8 <.L51>: - 1b8: 01954683 lbu a3,25(a0) - 1bc: 02e60633 mul a2,a2,a4 - 1c0: 40c787b3 sub a5,a5,a2 - 1c4: 04068e63 beqz a3,220 <.L52> - 1c8: 01b54883 lbu a7,27(a0) - 1cc: 4117d8b3 sra a7,a5,a7 - -000001d0 <.L53>: - 1d0: 03180833 mul a6,a6,a7 - 1d4: 0145ae03 lw t3,20(a1) - 1d8: 0105a683 lw a3,16(a1) - 1dc: 00c5a603 lw a2,12(a1) - 1e0: 00452303 lw t1,4(a0) - 1e4: 00852503 lw a0,8(a0) - 1e8: 01c70733 add a4,a4,t3 - 1ec: 00d886b3 add a3,a7,a3 - 1f0: 410787b3 sub a5,a5,a6 - 1f4: 00c78633 add a2,a5,a2 - 1f8: 000300e7 jalr t1 - 1fc: 00100793 li a5,1 - 200: 0007806b 0x7806b - 204: 03c12083 lw ra,60(sp) - 208: 03812403 lw s0,56(sp) - 20c: 03412483 lw s1,52(sp) - 210: 03012903 lw s2,48(sp) - 214: 02c12983 lw s3,44(sp) - 218: 04010113 addi sp,sp,64 - 21c: 00008067 ret - -00000220 <.L52>: - 220: 0307c8b3 div a7,a5,a6 - 224: fadff06f j 1d0 <.L53> - -00000228 <.L50>: - 228: 02c7c733 div a4,a5,a2 - 22c: f8dff06f j 1b8 <.L51> - -Disassembly of section .comment: - -00000000 <.comment>: - 0: 4700 lw s0,8(a4) - 2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm - 6: 4728 lw a0,72(a4) - 8: 554e lw a0,240(sp) - a: 2029 jal 14 - c: 2e39 jal 32a <.L50+0x102> - e: 2e32 fld ft8,264(sp) - 10: 0030 addi a2,sp,8 - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2541 jal 680 <.L50+0x458> - 2: 0000 unimp - 4: 7200 flw fs0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <.riscv.attributes+0x14> - c: 0000001b 0x1b - 10: 1004 addi s1,sp,32 - 12: 7205 lui tp,0xfffe1 - 14: 3376 fld ft6,376(sp) - 16: 6932 flw fs2,12(sp) - 18: 7032 flw ft0,44(sp) - 1a: 5f30 lw a2,120(a4) - 1c: 326d jal fffff9c6 <.L50+0xfffff79e> - 1e: 3070 fld fa2,224(s0) - 20: 665f 7032 0030 0x307032665f From 6c5032365fbead2fde511c558bb9bfbc31300ea8 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Mar 2021 22:02:44 -0500 Subject: [PATCH 7/7] build fix --- runtime/Makefile | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/runtime/Makefile b/runtime/Makefile index b575f223..ba9d1366 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -12,28 +12,24 @@ PROJECT = libvortexrt SRCS = ./src/vx_start.S ./src/vx_print.S ./src/vx_print.c ./src/vx_spawn.c -OBJS := $(SRCS:.S=.o) $(SRCS:.c=.o) +OBJS := $(addsuffix .o, $(notdir $(SRCS))) all: $(PROJECT).a $(PROJECT).dump -$(PROJECT).a: $(OBJS) - $(AR) rc $(PROJECT).a $^ - $(PROJECT).dump: $(PROJECT).a $(DP) -D $(PROJECT).a > $(PROJECT).dump -%.o: src/%.S - $(CC) $(CFLAGS) -c -o $@ $< +%.S.o: src/%.S + $(CC) $(CFLAGS) -c $< -o $@ -%.o: src/%.c - $(CC) $(CFLAGS) -c -o $@ $< +%.c.o: src/%.c + $(CC) $(CFLAGS) -c $< -o $@ + +$(PROJECT).a: $(OBJS) + $(AR) rc $(PROJECT).a $^ .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.a *.o *.dump .depend - -ifneq ($(MAKECMDGOALS),clean) - -include .depend -endif \ No newline at end of file + rm -rf *.a *.o *.dump .depend \ No newline at end of file