fixed loader script stack setup

hw/rtl/VX_config.vh

@@ -32,7 +32,7 @@
 `endif
 
 `ifndef SM_ENABLE
-`define SM_ENABLE 0
+`define SM_ENABLE 1
 `endif
 
 `ifndef GLOBAL_BLOCK_SIZE
@@ -47,14 +47,14 @@
 `define STARTUP_ADDR 32'h80000000
 `endif
 
-`ifndef SHARED_MEM_BASE_ADDR
-`define SHARED_MEM_BASE_ADDR 32'h6FFFF000
-`endif
-
 `ifndef IO_BUS_BASE_ADDR
 `define IO_BUS_BASE_ADDR 32'hFF000000
 `endif
 
+`ifndef SHARED_MEM_BASE_ADDR
+`define SHARED_MEM_BASE_ADDR `IO_BUS_BASE_ADDR
+`endif
+
 `ifndef IO_BUS_ADDR_COUT
 `define IO_BUS_ADDR_COUT 32'hFFFFFFFC
 `endif
@@ -139,16 +139,6 @@
 `define CSR_FRM         12'h002
 `define CSR_FCSR        12'h003
 
-// SIMT CSRs
-`define CSR_LTID        12'h020
-`define CSR_LWID        12'h021
-`define CSR_GTID        12'h022
-`define CSR_GWID        12'h023
-`define CSR_GCID        12'h024
-`define CSR_NT          12'h025
-`define CSR_NW          12'h026
-`define CSR_NC          12'h027
-
 `define CSR_SATP        12'h180
 
 `define CSR_PMPCFG0     12'h3A0
@@ -236,6 +226,19 @@
 `define CSR_MIMPID      12'hF13
 `define CSR_MHARTID     12'hF14
 
+// User SIMT CSRs
+`define CSR_WTID        12'hCC0
+`define CSR_LTID        12'hCC1
+`define CSR_GTID        12'hCC2
+`define CSR_LWID        12'hCC3
+`define CSR_GWID        `CSR_MHARTID
+`define CSR_GCID        12'hCC5
+
+// Machine SIMT CSRs
+`define CSR_NT          12'hFC0
+`define CSR_NW          12'hFC1
+`define CSR_NC          12'hFC2
+
 // Pipeline Queues ////////////////////////////////////////////////////////////
 
 // Size of instruction queue
@@ -324,9 +327,14 @@
 
 // SM Configurable Knobs //////////////////////////////////////////////////////
 
+// Size of cache block in bytes
+`ifndef SM_BLOCK_SIZE
+`define SM_BLOCK_SIZE 1024
+`endif
+
 // Size of cache in bytes
 `ifndef SMEM_SIZE
-`define SMEM_SIZE 8192
+`define SMEM_SIZE (`NUM_WARPS * `NUM_THREADS * `SM_BLOCK_SIZE)
 `endif
 
 // Number of banks

hw/rtl/VX_csr_data.v

@@ -110,9 +110,10 @@ module VX_csr_data #(
             `CSR_FCSR      : read_data_r = 32'(csr_fcsr[read_wid]);
 
             `CSR_LWID      : read_data_r = 32'(read_wid);
+            `CSR_WTID      ,
             `CSR_LTID      ,
             `CSR_GTID      ,
-            `CSR_MHARTID   ,
+            /*`CSR_MHARTID ,*/
             `CSR_GWID      : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid);
             `CSR_GCID      : read_data_r = CORE_ID;
             `CSR_NT        : read_data_r = `NUM_THREADS;

hw/rtl/VX_csr_unit.v

@@ -120,8 +120,9 @@ module VX_csr_unit #(
     );
 
     for (genvar i = 0; i < `NUM_THREADS; i++) begin
-        assign csr_pipe_rsp_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i : 
-                                         (csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) : 
+        assign csr_pipe_rsp_if.data[i] = (csr_addr_s1 == `CSR_WTID) ? i : 
+                                         (csr_addr_s1 == `CSR_LTID 
+                                       || csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) : 
                                                                       csr_read_data_s1;
     end         
 

hw/rtl/VX_define.vh

@@ -319,7 +319,7 @@
 `define SCACHE_ID               (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2)
 
 // Block size in bytes
-`define SBANK_LINE_SIZE         4 
+`define SBANK_LINE_SIZE         `SM_BLOCK_SIZE 
 
 // Word size in bytes
 `define SWORD_SIZE              4