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tex_unit refactoring

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This commit is contained in:
Blaise Tine
2021-05-28 13:29:47 -07:00
parent 1326538e5b
commit e41a16cb58
10 changed files with 250 additions and 314 deletions
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101
hw/rtl/tex_unit/VX_tex_memory.v
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@@ -1,7 +1,8 @@
`include "VX_tex_define.vh"
module VX_tex_memory #(
parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1
parameter REQ_INFO_WIDTH = 1,
parameter NUM_REQS = 1
) (
input wire clk,
input wire reset,
@@ -12,36 +13,32 @@ module VX_tex_memory #(
// inputs
input wire req_valid,
input wire [`NW_BITS-1:0] req_wid,
input wire [`NUM_THREADS-1:0] req_tmask,
input wire [31:0] req_PC,
input wire [NUM_REQS-1:0] req_tmask,
input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [`TEX_STRIDE_BITS-1:0] req_stride,
input wire [`NUM_THREADS-1:0][3:0][31:0] req_addr,
input wire [NUM_REQS-1:0][3:0][31:0] req_addr,
input wire [REQ_INFO_WIDTH-1:0] req_info,
output wire req_ready,
// outputs
output wire rsp_valid,
output wire [`NW_BITS-1:0] rsp_wid,
output wire [`NUM_THREADS-1:0] rsp_tmask,
output wire [31:0] rsp_PC,
output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_data,
output wire [NUM_REQS-1:0] rsp_tmask,
output wire [NUM_REQS-1:0][3:0][31:0] rsp_data,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
input wire rsp_ready
);
`UNUSED_PARAM (CORE_ID)
localparam RSP_CTR_W = $clog2(`NUM_THREADS * 4 + 1);
localparam RSP_CTR_W = $clog2(NUM_REQS * 4 + 1);
wire [3:0] dup_reqs;
wire [3:0][`NUM_THREADS-1:0][29:0] req_addr_w;
wire [3:0][`NUM_THREADS-1:0][1:0] align_offs;
wire [3:0][NUM_REQS-1:0][29:0] req_addr_w;
wire [3:0][NUM_REQS-1:0][1:0] align_offs;
// reorder address into quads
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < 4; ++j) begin
assign req_addr_w[j][i] = req_addr[i][j][31:2];
assign align_offs[j][i] = req_addr[i][j][1:0];
@@ -51,8 +48,8 @@ module VX_tex_memory #(
// find duplicate addresses
for (genvar i = 0; i < 4; ++i) begin
wire [`NUM_THREADS-1:0] addr_matches;
for (genvar j = 0; j < `NUM_THREADS; j++) begin
wire [NUM_REQS-1:0] addr_matches;
for (genvar j = 0; j < NUM_REQS; j++) begin
assign addr_matches[j] = (req_addr_w[i][0] == req_addr_w[i][j]) || ~req_tmask[j];
end
assign dup_reqs[i] = req_tmask[0] && (& addr_matches);
@@ -62,20 +59,18 @@ module VX_tex_memory #(
wire reqq_push, reqq_pop, reqq_empty, reqq_full;
wire [3:0][`NUM_THREADS-1:0][29:0] q_req_addr;
wire [`NW_BITS-1:0] q_req_wid;
wire [`NUM_THREADS-1:0] q_req_tmask;
wire [31:0] q_req_PC;
wire [3:0][NUM_REQS-1:0][29:0] q_req_addr;
wire [NUM_REQS-1:0] q_req_tmask;
wire [`TEX_FILTER_BITS-1:0] q_req_filter;
wire [REQ_INFO_WIDTH-1:0] q_req_info;
wire [`TEX_STRIDE_BITS-1:0] q_req_stride;
wire [3:0][`NUM_THREADS-1:0][1:0] q_align_offs;
wire [3:0][NUM_REQS-1:0][1:0] q_align_offs;
wire [3:0] q_dup_reqs;
assign reqq_push = req_valid && req_ready;
VX_fifo_queue #(
.DATAW ((`NUM_THREADS * 4 * 30) + `NW_BITS + `NUM_THREADS + 32 + REQ_INFO_WIDTH + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * `NUM_THREADS * 2) + 4),
.DATAW ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFO_WIDTH + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * NUM_REQS * 2) + 4),
.SIZE (`LSUQ_SIZE),
.BUFFERED (1)
) req_queue (
@@ -83,8 +78,8 @@ module VX_tex_memory #(
.reset (reset),
.push (reqq_push),
.pop (reqq_pop),
.data_in ({req_addr_w, req_wid, req_tmask, req_PC, req_info, req_filter, req_stride, align_offs, dup_reqs}),
.data_out ({q_req_addr, q_req_wid, q_req_tmask, q_req_PC, q_req_info, q_req_filter, q_req_stride, q_align_offs, q_dup_reqs}),
.data_in ({req_addr_w, req_tmask, req_info, req_filter, req_stride, align_offs, dup_reqs}),
.data_out ({q_req_addr, q_req_tmask, q_req_info, q_req_filter, q_req_stride, q_align_offs, q_dup_reqs}),
.empty (reqq_empty),
.full (reqq_full),
`UNUSED_PIN (alm_full),
@@ -100,7 +95,7 @@ module VX_tex_memory #(
wire req_texel_valid;
wire sent_all_ready, last_texel_sent;
wire req_texel_dup;
wire [`NUM_THREADS-1:0][29:0] req_texel_addr;
wire [NUM_REQS-1:0][29:0] req_texel_addr;
reg [1:0] req_texel_idx;
reg req_texels_done;
@@ -129,9 +124,9 @@ module VX_tex_memory #(
// DCache Request
reg [`NUM_THREADS-1:0] texel_sent_mask;
wire [`NUM_THREADS-1:0] dcache_req_fire;
wire [`NUM_THREADS-1:0] req_dup_mask;
reg [NUM_REQS-1:0] texel_sent_mask;
wire [NUM_REQS-1:0] dcache_req_fire;
wire [NUM_REQS-1:0] req_dup_mask;
assign dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
@@ -146,30 +141,31 @@ module VX_tex_memory #(
end
end
assign req_dup_mask = {{(`NUM_THREADS-1){~req_texel_dup}}, 1'b1};
assign req_dup_mask = {{(NUM_REQS-1){~req_texel_dup}}, 1'b1};
assign dcache_req_if.valid = {`NUM_THREADS{req_texel_valid}} & q_req_tmask & req_dup_mask & ~texel_sent_mask;
assign dcache_req_if.rw = {`NUM_THREADS{1'b0}};
assign dcache_req_if.valid = {NUM_REQS{req_texel_valid}} & q_req_tmask & req_dup_mask & ~texel_sent_mask;
assign dcache_req_if.rw = {NUM_REQS{1'b0}};
assign dcache_req_if.addr = req_texel_addr;
assign dcache_req_if.byteen = {`NUM_THREADS{4'b1111}};
assign dcache_req_if.byteen = {NUM_REQS{4'b1111}};
assign dcache_req_if.data = 'x;
`ifdef DBG_CACHE_REQ_INFO
assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, req_texel_idx}};
wire [`NW_BITS-1:0] q_req_wid;
wire [31:0] q_req_PC;
assign {q_req_wid, q_req_PC} = q_req_info[`NW_BITS+32-1:0];
assign dcache_req_if.tag = {NUM_REQS{q_req_PC, q_req_wid, req_texel_idx}};
`else
assign dcache_req_if.tag = {`NUM_THREADS{req_texel_idx}};
`UNUSED_VAR (q_req_wid)
`UNUSED_VAR (q_req_PC)
assign dcache_req_if.tag = {NUM_REQS{req_texel_idx}};
`endif
// Dcache Response
reg [3:0][`NUM_THREADS-1:0][31:0] rsp_texels, rsp_texels_n;
wire [`NUM_THREADS-1:0][3:0][31:0] rsp_texels_qual;
reg [`NUM_THREADS-1:0][31:0] rsp_data_qual;
reg [3:0][NUM_REQS-1:0][31:0] rsp_texels, rsp_texels_n;
wire [NUM_REQS-1:0][3:0][31:0] rsp_texels_qual;
reg [NUM_REQS-1:0][31:0] rsp_data_qual;
reg [RSP_CTR_W-1:0] rsp_rem_ctr;
wire [`NUM_THREADS-1:0] rsp_cur_tmask;
wire [$clog2(`NUM_THREADS + 1)-1:0] rsp_cur_cnt;
wire [NUM_REQS-1:0] rsp_cur_tmask;
wire [$clog2(NUM_REQS + 1)-1:0] rsp_cur_cnt;
wire dcache_rsp_fire;
wire [1:0] rsp_texel_idx;
wire rsp_texel_dup;
@@ -184,7 +180,7 @@ module VX_tex_memory #(
assign rsp_cur_cnt = $countones(rsp_cur_tmask);
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
wire [31:0] src_mask = {32{dcache_rsp_if.valid[i]}};
wire [31:0] src_data = ((i == 0 || rsp_texel_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i]) & src_mask;
@@ -229,7 +225,7 @@ module VX_tex_memory #(
end
end
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < 4; ++j) begin
assign rsp_texels_qual[i][j] = rsp_texels_n[j][i];
end
@@ -242,43 +238,48 @@ module VX_tex_memory #(
assign reqq_pop = rsp_texels_done && ~stall_out;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + (4 * `NUM_THREADS * 32) + REQ_INFO_WIDTH),
.DATAW (1 + NUM_REQS + REQ_INFO_WIDTH + (4 * NUM_REQS * 32)),
.RESETW (1)
) rsp_pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({rsp_texels_done, q_req_wid, q_req_tmask, q_req_PC, rsp_texels_qual, q_req_info}),
.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_data, rsp_info})
.data_in ({rsp_texels_done, q_req_tmask, q_req_info, rsp_texels_qual}),
.data_out ({rsp_valid, rsp_tmask, rsp_info, rsp_data})
);
// Can accept new cache response?
assign dcache_rsp_if.ready = ~stall_out || (rsp_rem_ctr != RSP_CTR_W'(rsp_cur_cnt));
`ifdef DBG_PRINT_TEX
always @(posedge clk) begin
wire [`NW_BITS-1:0] req_wid, rsp_wid;
wire [31:0] req_PC, rsp_PC;
assign {req_wid, req_PC} = req_info[`NW_BITS+32-1:0];
assign {rsp_wid, rsp_PC} = rsp_info[`NW_BITS+32-1:0];
always @(posedge clk) begin
if ((| dcache_req_fire)) begin
$write("%t: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=",
$time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, dcache_req_if.tag);
`PRINT_ARRAY1D(req_texel_addr, `NUM_THREADS);
`PRINT_ARRAY1D(req_texel_addr, NUM_REQS);
$write(", is_dup=%b\n", req_texel_dup);
end
if (dcache_rsp_fire) begin
$write("%t: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=",
$time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.valid, dcache_rsp_if.tag);
`PRINT_ARRAY1D(rsp_data_qual, `NUM_THREADS);
`PRINT_ARRAY1D(rsp_data_qual, NUM_REQS);
$write("\n");
end
if (req_valid && req_ready) begin
$write("%t: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, stride=%0d, addr=",
$time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_stride);
`PRINT_ARRAY2D(req_addr, 4, `NUM_THREADS);
`PRINT_ARRAY2D(req_addr, 4, NUM_REQS);
$write("\n");
end
if (rsp_valid && rsp_ready) begin
$write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask);
`PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS);
`PRINT_ARRAY2D(rsp_data, 4, NUM_REQS);
$write("\n");
end
end