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erge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis

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Blaise Tine
2020-05-19 17:40:45 -07:00
parent c37e6e2207 cad92bbeb1
commit e3bead147a
1 changed files with 5 additions and 4 deletions
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9
hw/rtl/VX_scheduler.v
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@@ -42,10 +42,11 @@ module VX_scheduler (
wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual;
assign schedule_delay = ((rename_valid) && (| bckE_req_if.valid)) assign schedule_delay = (|bckE_req_if.valid) &&
|| (memory_delay && is_mem) ((rename_valid ) ||
|| (gpr_stage_delay && (is_mem || is_exec)) (memory_delay && is_mem) ||
|| (exec_delay && is_exec); (gpr_stage_delay && (is_mem || is_exec)) ||
(exec_delay && is_exec));
integer i, w; integer i, w;