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Merge branch 'master' into graphics

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This commit is contained in:
Blaise Tine
2021-10-15 19:32:11 -07:00
parent 668cfb5da4 e2b5799a01
commit e380ded5e1
542 changed files with 124552 additions and 18682 deletions
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18
hw/syn/opae/Makefile
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@@ -26,11 +26,11 @@ DBG_FLAGS += -DDBG_CACHE_REQ_INFO
CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG8 := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG32 := -DNUM_CLUSTERS=8 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
CONFIG4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS)
CONFIG8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE=1 -DL3_ENABLE=0 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL2_CACHE_SIZE=131072 $(CONFIGS)
CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS)
CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=262144 $(CONFIGS)
CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_SIZE=8192 -DDCACHE_SIZE=8192 -DL3_CACHE_SIZE=524288 $(CONFIGS)
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
@@ -55,7 +55,11 @@ ifdef PERF
CFLAGS += -DPERF_ENABLE
endif
all: ase-1c
all: vortex_afu.h ase-1c
# AFU info from JSON file, including AFU UUID
vortex_afu.h: vortex_afu.json
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
$(BUILD_DIR)_ase_1c/Makefile:
afu_sim_setup -s setup.cfg $(BUILD_DIR)_ase_1c
@@ -197,4 +201,4 @@ clean-fpga-32c:
clean-fpga-64c:
rm -rf $(BUILD_DIR)_fpga_64c sources.txt
clean: clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c
clean: vortex_afu.h clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c clean-fpga-8c clean-fpga-16c clean-fpga-32c clean-fpga-64c

16
hw/syn/opae/README
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@@ -63,13 +63,13 @@ qsub-sim
make ase
# tests
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t0
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n1 -t1
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/basic/basic -n16
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/demo/demo -n16
./run_ase.sh build_ase_arria10_1c ../../../driver/tests/dogfood/dogfood -n16
./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/vecadd/vecadd
./run_ase.sh build_ase_arria10_1c ../../../benchmarks/opencl/sgemm/sgemm -n4
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t0
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n1 -t1
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/basic/basic -n16
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/demo/demo -n16
./run_ase.sh build_arria10_ase_1c ../../../tests/regression/dogfood/dogfood -n16
./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/vecadd/vecadd
./run_ase.sh build_arria10_ase_1c ../../../tests/opencl/sgemm/sgemm -n4
# modify "vsim_run.tcl" to dump VCD trace
vcd file trace.vcd
@@ -82,7 +82,7 @@ tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt
# compress log trace
tar -zcvf run.log.tar.gz run.log
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
tar -cvjf trace.vcd.tar.bz2 build_ase_arria10_1c/work/run.log build_ase_arria10_1c/work/trace.vcd
tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/work/run.log build_arria10_ase_1c/work/trace.vcd
# decompress log trace
tar -zxvf vortex.vcd.tar.gz

7
hw/syn/opae/fpga_prog.sh Executable file
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@@ -0,0 +1,7 @@
#!/bin/bash
# FPGA programming
# first argument is the bitstream
echo "fpgaconf --bus 0xaf $1"
fpgaconf --bus 0xaf $1

2
hw/syn/opae/gen_sources.sh
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@@ -1,6 +1,6 @@
#!/bin/bash
exclude_list="VX_fpu_fpnew.v"
exclude_list="VX_fpu_fpnew.sv"
macros=()
includes=()

2
hw/syn/opae/run_ase.sh
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@@ -35,5 +35,5 @@ done
# run application
pushd $PROGRAM_DIR
echo " [DBG] running ./$PROGRAM $*"
ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $*
ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/asesim:$LD_LIBRARY_PATH ./$PROGRAM $*
popd

12
hw/syn/opae/vortex_afu.qsf
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@@ -23,12 +23,12 @@ set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name USE_HIGH_SPEED_ADDER ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
#set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100