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Fixed pulling signals from different stages

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This commit is contained in:
felsabbagh3
2020-03-29 18:17:01 -07:00
parent d31116d584
commit e31b2d6d7e
1 changed files with 4 additions and 2 deletions
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6
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -95,7 +95,8 @@ module VX_cache_dram_req_arb
); );
wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank; wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank;
wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp; // wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb( VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb(
.valids(use_wb_valid), .valids(use_wb_valid),
.index (dwb_bank), .index (dwb_bank),
@@ -112,6 +113,7 @@ module VX_cache_dram_req_arb
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK; assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = BANK_LINE_SIZE_BYTES; assign dram_req_size = BANK_LINE_SIZE_BYTES;
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0; // assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;
assign dram_req_because_of_wb = 0;
endmodule endmodule