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MULTICORE WITH L2 WORKING

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This commit is contained in:
felsabbagh3
2020-03-09 01:17:11 -07:00
parent a539630a0a
commit e2ffbcf14b
28 changed files with 642 additions and 557 deletions
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127
rtl/VX_cache/VX_bank.v
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@@ -1,5 +1,5 @@
`include "VX_cache_config.v"
`include "VX_define.v"
module VX_bank
#(
// Size of cache in bytes
@@ -54,13 +54,13 @@ module VX_bank
input wire delay_req,
input wire [NUMBER_REQUESTS-1:0] bank_valids,
input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [1:0] bank_wb,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [31:0] bank_pc,
input wire [`NW_M1:0] bank_warp_num,
input wire [2:0] bank_mem_read,
input wire [2:0] bank_mem_write,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
output wire reqq_full,
// Output Core WB
@@ -70,8 +70,9 @@ module VX_bank
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_M1:0] bank_wb_warp_num,
output wire [31:0] bank_wb_data,
output wire [`WORD_SIZE_RNG] bank_wb_data,
output wire [31:0] bank_wb_pc,
output wire [31:0] bank_wb_address,
// Dram Fill Requests
output wire dram_fill_req,
@@ -83,25 +84,18 @@ module VX_bank
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
input wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram WB Requests
input wire dram_wb_queue_pop,
output wire dram_wb_req,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data,
output wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_wb_req_data,
// Snp Request
input wire snp_req,
input wire[31:0] snp_req_addr,
// Lower Level Cache Response
input wire llvq_pop,
output wire llvq_valid,
output wire[31:0] llvq_res_addr,
output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data,
output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_res_tid
input wire[31:0] snp_req_addr
);
@@ -132,12 +126,12 @@ module VX_bank
wire dfpq_empty;
wire dfpq_full;
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dfpq_filldata_st0;
reg dfpq_hazard_st0;
assign dram_fill_accept = !dfpq_full;
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(DFPQ_SIZE)) dfp_queue(
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
@@ -155,7 +149,7 @@ module VX_bank
wire reqq_req_st0;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0;
wire [31:0] reqq_req_addr_st0;
wire [31:0] reqq_req_writeword_st0;
wire [`WORD_SIZE_RNG] reqq_req_writeword_st0;
wire [4:0] reqq_req_rd_st0;
wire [1:0] reqq_req_wb_st0;
wire [`NW_M1:0] reqq_req_warp_num_st0;
@@ -221,7 +215,7 @@ module VX_bank
wire mrvq_valid_st0;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
wire [31:0] mrvq_addr_st0;
wire [31:0] mrvq_writeword_st0;
wire [`WORD_SIZE_RNG] mrvq_writeword_st0;
wire [4:0] mrvq_rd_st0;
wire [1:0] mrvq_wb_st0;
wire [31:0] miss_resrv_pc_st0;
@@ -232,7 +226,7 @@ module VX_bank
wire miss_add;
wire[31:0] miss_add_addr;
wire[31:0] miss_add_data;
wire[`WORD_SIZE_RNG] miss_add_data;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
@@ -311,8 +305,8 @@ module VX_bank
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
assign reqq_pop = !mrvq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
assign snrq_pop = !reqq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
integer st1_cycle;
@@ -338,8 +332,8 @@ module VX_bank
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [31:0] qual_addr_st0;
wire [31:0] qual_writeword_st0;
wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0;
wire [`WORD_SIZE_RNG] qual_writeword_st0;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] qual_writedata_st0;
wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
wire qual_going_to_write_st0;
wire qual_is_snp;
@@ -348,14 +342,21 @@ module VX_bank
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
assign qual_is_fill_st0 = dfpq_pop;
// always @(*) begin
// if (qual_is_fill_st0 && (FUNC_ID == 3)) begin
// $display("WHAT THE FUCK FUNC_ID: %x", FUNC_ID);
// end
// end
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
@@ -364,11 +365,7 @@ module VX_bank
snrq_pop ? snrq_addr_st0 :
0;
assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
reqq_pop ? reqq_req_writeword_st0 :
0;
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
@@ -387,7 +384,11 @@ module VX_bank
32'h0;
assign qual_is_snp = snrq_pop ? 1 : 0;
VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1 + 32)) s0_1_c0 (
assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
reqq_pop ? reqq_req_writeword_st0 :
0;
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -399,7 +400,7 @@ module VX_bank
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1 + 32)) s0_1_cc (
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -411,8 +412,8 @@ module VX_bank
endgenerate
wire[31:0] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e;
wire[`WORD_SIZE_RNG] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st1e;
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
@@ -424,7 +425,7 @@ module VX_bank
wire [`NW_M1:0] warp_num_st1e;
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e;
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
@@ -486,9 +487,9 @@ module VX_bank
wire valid_st2;
wire[31:0] addr_st2;
wire[31:0] writeword_st2;
wire[31:0] readword_st2;
wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2;
wire[`WORD_SIZE_RNG] writeword_st2;
wire[`WORD_SIZE_RNG] readword_st2;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
@@ -498,18 +499,19 @@ module VX_bank
wire is_snp_st2;
wire [31:0] pc_st2;
VX_generic_register #(.N( 1 + 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32)) st_1e_2 (
VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_SIZE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
);
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2 && !stall_bank_pipe && !mrvq_full && !(dirty_st2 && dwbq_full);
assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (dram_fill_req && dram_fill_req_queue_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
@@ -517,8 +519,8 @@ module VX_bank
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full & !llvq_full;
wire [31:0] cwbq_data = readword_st2;
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
@@ -528,15 +530,15 @@ module VX_bank
wire cwbq_full;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc}),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.pop (bank_wb_pop),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc}),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}),
.empty (cwbq_empty),
.full (cwbq_full)
);
@@ -544,7 +546,7 @@ module VX_bank
// Enqueue to DWB Queue
wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(!fill_saw_dirty_st2 && mrvq_full);
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire dwbq_full;
@@ -588,7 +590,7 @@ module VX_bank
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(DWBQ_SIZE)) dwb_queue(
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),
@@ -602,29 +604,8 @@ module VX_bank
);
// Lower Cache Hit
wire llvq_empty;
wire llvq_full;
wire llvq_push = valid_st2 && !miss_st2 && !llvq_full && !cwbq_full;
wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2;
wire[31:0] llvq_addr = addr_st2;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid;
assign llvq_valid = !llvq_empty;
VX_generic_queue_ll #(.DATAW(`vx_clog2(NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(LLVQ_SIZE)) llv_queue(
.clk (clk),
.reset (reset),
.push (llvq_push),
.in_data ({llvq_tid , llvq_addr , llvq_push_data}),
.pop (llvq_pop),
.out_data({llvq_res_tid, llvq_res_addr, llvq_res_data}),
.empty (llvq_empty),
.full (llvq_full)
);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (llvq_push && llvq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full);
endmodule