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refactor synthesis scripts + fixed quartus ram read-after-write bypass

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This commit is contained in:
Blaise Tine
2020-06-16 11:45:47 -07:00
parent 9850a1f890
commit e2e1b63e14
22 changed files with 347 additions and 200 deletions
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4
hw/syn/quartus/top/Makefile
View File

@@ -8,7 +8,7 @@ FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae"
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae;../../../opae/ccip" -macro "NOPAE"
syn.chg:
$(STAMP) syn.chg

48
hw/syn/quartus/top/project.tcl
View File

@@ -1,30 +1,56 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
set options {
{ "project.arg" "" "Project name" }
{ "family.arg" "" "Device family name" }
{ "device.arg" "" "Device name" }
{ "top.arg" "" "Top level module" }
{ "src.arg" "" "Verilog source file" }
{ "inc.arg" "" "Include path (optional)" }
{ "sdc.arg" "" "Timing Design Constraints file (optional)" }
{ "set.arg" "" "Macro value (optional)" }
}
set q_args_orig $quartus(args)
array set opts [::cmdline::getoptions quartus(args) $options]
# Verify required parameters
set requiredParameters {project family device top src}
foreach p $requiredParameters {
if {$opts($p) == ""} {
puts stderr "Missing required parameter: -$p"
exit 1
}
}
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set idx 0
foreach arg $q_args_orig {
incr idx
if [string match "-src" $arg] {
set_global_assignment -name VERILOG_FILE [lindex $q_args_orig $idx]
}
if [string match "-inc" $arg] {
set_global_assignment -name SEARCH_PATH [lindex $q_args_orig $idx]
}
if [string match "-sdc" $arg] {
set_global_assignment -name SDC_FILE [lindex $q_args_orig $idx]
}
if [string match "-set" $arg] {
set_global_assignment -name VERILOG_MACRO [lindex $q_args_orig $idx]
}
}
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]