diff --git a/rtl/VX_gpr.v b/rtl/VX_gpr.v
index 96592049..4a7be49c 100644
--- a/rtl/VX_gpr.v
+++ b/rtl/VX_gpr.v
@@ -44,7 +44,7 @@ module VX_gpr (
 	wire cena_1  = (VX_gpr_read.rs1 == 0);
 	wire cena_2  = (VX_gpr_read.rs2 == 0);
 
-	// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
+	wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
 	/* verilator lint_off PINCONNECTEMPTY */
    rf2_32x128_wm1 first_ram (
          .CENYA(),
diff --git a/syn/syn.tcl b/syn/syn.tcl
index 80ddeb42..1877bfa8 100755
--- a/syn/syn.tcl
+++ b/syn/syn.tcl
@@ -19,6 +19,10 @@ set_ideal_network [get_ports clk]
 set_max_fanout 20 [get_ports reset]
 set_false_path -from [get_ports reset]
 
+set_register_merging Vortex FALSE
+set compile_seqmap_propagate_constants false
+set compile_seqmap_propagate_high_effort false
+
 compile_ultra -no_autoungroup
 ungroup -all -flatten
 uniquify