minor updates

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/Makefile

@@ -0,0 +1,12 @@
+all: RUNFILE
+
+# -LDFLAGS '-lsystemc'
+VERILATOR:
+	verilator rf2_32x128_wm1_rtl.v -cc --exe testbench.cpp --Wno-UNOPTFLAT --Wno-WIDTH --Wno-STMTDLY --Wno-UNSIGNED -LDFLAGS '-lsystemc'
+
+
+RUNFILE: VERILATOR
+	(cd obj_dir && make -j -f Vrf2_32x128_wm1_rtl.mk)
+
+clean:
+	rm obj_dir/*

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/env_vsim

@@ -0,0 +1 @@
+source /tools/mentor/modelsim/ms106a/cshrc.modelsim

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib

@@ -0,0 +1,358 @@
+/* logicvision_memcomp Version: c0.1.5-EAC */
+/* common_memcomp Version: c0.1.2-EAC */
+/* lang compiler Version: 4.5.1-EAC Nov  6 2014 16:10:45 */
+//
+//       CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+//      
+//       Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+//      
+//       Use of this Software is subject to the terms and conditions of the
+//       applicable license agreement with ARM Physical IP, Inc.
+//       In addition, this Software is protected by patents, copyright law 
+//       and international treaties.
+//      
+//       The copyright notice(s) in this Software does not indicate actual or
+//       intended publication of this Software.
+//
+//      logicvision model for High Capacity Two Port Register File SVT MVT Compiler
+//
+//      Instance Name:              rf2_32x128_wm1
+//      Words:                      32
+//      Bits:                       128
+//      Mux:                        2
+//      Drive:                      6
+//      Write Mask:                 On
+//      Extra Margin Adjustment:    On
+//      Redundant Rows:             0
+//      Redundant Columns:          2
+//      Test Muxes                  On
+//
+//      Creation Date:  Mon Oct 14 17:01:15 2019
+//      Version: 	r0p0
+//
+//      Modeling Assumptions: 
+//
+//      Modeling Limitations: None
+//
+//      Known Bugs: None.
+//
+//      Known Work Arounds: N/A
+//
+MemoryTemplate (rf2_32x128_wm1) {
+	Algorithm : SmarchChkbvcd;
+	DataOutStage : None;
+	LogicalPorts : 1R1W;
+	BitGrouping : 1;
+	MemoryType : SRAM;
+	MinHold : 0.5;
+	OperationSet : SyncWRvcd;
+	SelectDuringWriteThru : Off;
+	ShadowRead : On;
+	ShadowWrite : On;
+   ShadowWriteOk : On;
+        TransparentMode : None;
+        ObservationLogic: On;
+        InternalScanLogic: On;
+	CellName : rf2_32x128_wm1;
+	NumberOfWords : 32;
+	AddressCounter{
+		Function (Address) {
+			LogicalAddressMap{
+				ColumnAddress[0] : Address[0];
+				RowAddress[3:0] : Address[4:1];
+			}
+		}
+		Function (ColumnAddress) {
+			CountRange [0:1];
+			}
+		Function (RowAddress) {
+			CountRange [0:15];
+		}
+	}
+	PhysicalAddressMap{
+		ColumnAddress[0] : c[0];
+		RowAddress[0] : r[0];
+		RowAddress[1] : r[1];
+		RowAddress[2] : r[2];
+		RowAddress[3] : r[3];
+	}
+	PhysicalDataMap{
+		Data[0] : NOT d[0];
+		Data[1] : NOT d[1];
+		Data[2] : NOT d[2];
+		Data[3] : NOT d[3];
+		Data[4] : NOT d[4];
+		Data[5] : NOT d[5];
+		Data[6] : NOT d[6];
+		Data[7] : NOT d[7];
+		Data[8] : NOT d[8];
+		Data[9] : NOT d[9];
+		Data[10] : NOT d[10];
+		Data[11] : NOT d[11];
+		Data[12] : NOT d[12];
+		Data[13] : NOT d[13];
+		Data[14] : NOT d[14];
+		Data[15] : NOT d[15];
+		Data[16] : NOT d[16];
+		Data[17] : NOT d[17];
+		Data[18] : NOT d[18];
+		Data[19] : NOT d[19];
+		Data[20] : NOT d[20];
+		Data[21] : NOT d[21];
+		Data[22] : NOT d[22];
+		Data[23] : NOT d[23];
+		Data[24] : NOT d[24];
+		Data[25] : NOT d[25];
+		Data[26] : NOT d[26];
+		Data[27] : NOT d[27];
+		Data[28] : NOT d[28];
+		Data[29] : NOT d[29];
+		Data[30] : NOT d[30];
+		Data[31] : NOT d[31];
+		Data[32] : NOT d[32];
+		Data[33] : NOT d[33];
+		Data[34] : NOT d[34];
+		Data[35] : NOT d[35];
+		Data[36] : NOT d[36];
+		Data[37] : NOT d[37];
+		Data[38] : NOT d[38];
+		Data[39] : NOT d[39];
+		Data[40] : NOT d[40];
+		Data[41] : NOT d[41];
+		Data[42] : NOT d[42];
+		Data[43] : NOT d[43];
+		Data[44] : NOT d[44];
+		Data[45] : NOT d[45];
+		Data[46] : NOT d[46];
+		Data[47] : NOT d[47];
+		Data[48] : NOT d[48];
+		Data[49] : NOT d[49];
+		Data[50] : NOT d[50];
+		Data[51] : NOT d[51];
+		Data[52] : NOT d[52];
+		Data[53] : NOT d[53];
+		Data[54] : NOT d[54];
+		Data[55] : NOT d[55];
+		Data[56] : NOT d[56];
+		Data[57] : NOT d[57];
+		Data[58] : NOT d[58];
+		Data[59] : NOT d[59];
+		Data[60] : NOT d[60];
+		Data[61] : NOT d[61];
+		Data[62] : NOT d[62];
+		Data[63] : NOT d[63];
+		Data[64] : d[64];
+		Data[65] : d[65];
+		Data[66] : d[66];
+		Data[67] : d[67];
+		Data[68] : d[68];
+		Data[69] : d[69];
+		Data[70] : d[70];
+		Data[71] : d[71];
+		Data[72] : d[72];
+		Data[73] : d[73];
+		Data[74] : d[74];
+		Data[75] : d[75];
+		Data[76] : d[76];
+		Data[77] : d[77];
+		Data[78] : d[78];
+		Data[79] : d[79];
+		Data[80] : d[80];
+		Data[81] : d[81];
+		Data[82] : d[82];
+		Data[83] : d[83];
+		Data[84] : d[84];
+		Data[85] : d[85];
+		Data[86] : d[86];
+		Data[87] : d[87];
+		Data[88] : d[88];
+		Data[89] : d[89];
+		Data[90] : d[90];
+		Data[91] : d[91];
+		Data[92] : d[92];
+		Data[93] : d[93];
+		Data[94] : d[94];
+		Data[95] : d[95];
+		Data[96] : d[96];
+		Data[97] : d[97];
+		Data[98] : d[98];
+		Data[99] : d[99];
+		Data[100] : d[100];
+		Data[101] : d[101];
+		Data[102] : d[102];
+		Data[103] : d[103];
+		Data[104] : d[104];
+		Data[105] : d[105];
+		Data[106] : d[106];
+		Data[107] : d[107];
+		Data[108] : d[108];
+		Data[109] : d[109];
+		Data[110] : d[110];
+		Data[111] : d[111];
+		Data[112] : d[112];
+		Data[113] : d[113];
+		Data[114] : d[114];
+		Data[115] : d[115];
+		Data[116] : d[116];
+		Data[117] : d[117];
+		Data[118] : d[118];
+		Data[119] : d[119];
+		Data[120] : d[120];
+		Data[121] : d[121];
+		Data[122] : d[122];
+		Data[123] : d[123];
+		Data[124] : d[124];
+		Data[125] : d[125];
+		Data[126] : d[126];
+		Data[127] : d[127];
+	}
+	Port (AA[4:0]) {
+		Function : Address;
+		LogicalPort : A;
+		EmbeddedTestLogic {
+			TestInput : TAA[4:0];
+			TestOutput : AYA[4:0];
+		}
+	}
+	Port (QA[127:0]) {
+		Function : Data;
+		Direction : output;
+		LogicalPort : A;
+	}
+	Port (CENA) {
+		Function : ReadEnable;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENA;
+			TestOutput : CENYA;
+		}
+	}
+	Port (TENA) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+	}
+	Port (CLKA) {
+		Function : Clock;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAA[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMASA) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+  port (SEA){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIA[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOA[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+  port (DFTRAMBYP){
+          Function : ScanTest;
+          Direction : Input;
+          Polarity : ActiveHigh;
+  }
+	Port (AB[4:0]) {
+		Function : Address;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TAB[4:0];
+			TestOutput : AYB[4:0];
+		}
+	}
+	Port (DB[127:0]) {
+		Function : Data;
+		Direction : input;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TDB[127:0];
+		}
+	}
+	Port (WENB[127:0]) {
+		Function : GroupWriteEnable;
+                BitsPerWriteEnable: 1;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TWENB[127:0];
+			TestOutput : WENYB[127:0];
+		}
+	}
+	Port (CENB) {
+		Function : WriteEnable;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENB;
+			TestOutput : CENYB;
+		}
+	}
+	Port (TENB) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+	}
+	Port (CLKB) {
+		Function : Clock;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAB[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (COLLDISN) {
+             Function : None;
+             SafeValue : 1;
+             Direction : Input;
+             Polarity : ActiveLow;
+       }
+  port (SEB){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIB[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOB[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+	port (RET1N){
+		Function : None;
+		Direction : Input;
+		SafeValue : 1;
+		Polarity : Activelow;
+	}
+}

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:07 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     avm
+#   AMCI Version:                  2.0.4-EAC
+#   avm_memcomp Version:       2.3.7-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_32x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 4506
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS FF, CORNER FF_0P99V_0P99V_M40C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.99 0.99
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 5.92707e-05nF
+    VDDPE VSSE 6.01330e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 2.06670mA
+    VDDPE VSSE 7.00670mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 6.51978e-05nF
+    VDDPE VSSE 4.44480e-03nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 2.27337mA
+    VDDPE VSSE 40.32645mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 3.12285e-04nF
+    VDDPE VSSE 8.61142e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 5.75579mA
+    VDDPE VSSE 75.37331mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 9.25793e-05nF
+    VDDPE VSSE 3.63286e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 2.15420mA
+    VDDPE VSSE 42.96800mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 2.19705e-04nF
+    VDDPE VSSE 4.97856e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 4.56860mA
+    VDDPE VSSE 62.31700mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 8.97079e-06nF
+    VDDPE VSSE 1.11565e-02nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.54208mA
+    VDDPE VSSE 46.13168mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 8.97079e-06nF
+    VDDPE VSSE 1.11565e-02nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.54208mA
+    VDDPE VSSE 46.13168mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.88451e-05nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 4.76848e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 2.29200e-03mA
+    VDDPE VSSE 9.63200e-03mA
+  }
+  tsu 0.074586ns
+  ck2q_delay 0.386174ns
+  tr_q 0.012874ns
+  tf_q 0.014219ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat

@@ -0,0 +1,342 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:37 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     datatable
+#   AMCI Version:                  2.0.4-EAC
+#   datatable_memcomp Version:       2.3.2-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	ff_0p99v_0p99v_m40c
+S	N
+geomx     	21.9750   
+geomy     	414.8600  
+volt      	0.9900    
+temp      	-40.0000  
+# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.0756	
+ttcenacenya	0.0754	
+ttenacenyapu	0.1068	
+ttenacenyanu	0.1229	
+tdftrambypcenya	0.1215	
+taaaya	0.0649	
+ttaaaya	0.0657	
+ttenaayapu	0.1204	
+ttenaayanu	0.1113	
+tdftrambypaya	0.1102	
+tcenbcenyb	0.0776	
+ttcenbcenyb	0.0789	
+ttenbcenybpu	0.1132	
+ttenbcenybnu	0.1593	
+tdftrambypcenyb	0.1160	
+twenbwenyb	0.0831	
+ttwenbwenyb	0.0825	
+ttenbwenybpu	0.2299	
+ttenbwenybnu	0.2434	
+tdftrambypwenyb	0.1505	
+tabayb	0.0648	
+ttabayb	0.0652	
+ttenbaybpu	0.1534	
+ttenbaybnu	0.1525	
+tdftrambypayb	0.1080	
+taccqa_rd0	0.3873	
+taccqa_rd1	0.3869	
+taccqa_rd2	0.3863	
+taccqa_rd3	0.3862	
+taccqa_rd4	0.4256	
+taccqa_rd5	0.4537	
+taccqa_rd6	0.4889	
+taccqa_rd7	0.5169	
+taccqa_scan0	0.3873	
+taccqa_scan1	0.3869	
+taccqa_scan2	0.3863	
+taccqa_scan3	0.3862	
+taccqa_scan4	0.4256	
+taccqa_scan5	0.4537	
+taccqa_scan6	0.4889	
+taccqa_scan7	0.5169	
+tclkasoa_rd0	0.4029	
+tclkasoa_rd1	0.4026	
+tclkasoa_rd2	0.4019	
+tclkasoa_rd3	0.4018	
+tclkasoa_rd4	0.4412	
+tclkasoa_rd5	0.4693	
+tclkasoa_rd6	0.5045	
+tclkasoa_rd7	0.5325	
+tclkasoa_scan0	0.4029	
+tclkasoa_scan1	0.4026	
+tclkasoa_scan2	0.4019	
+tclkasoa_scan3	0.4018	
+tclkasoa_scan4	0.4412	
+tclkasoa_scan5	0.4693	
+tclkasoa_scan6	0.5045	
+tclkasoa_scan7	0.5325	
+tclkbsob	0.2114	
+# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	1.5204	
+kload_aya	1.2343	
+kload_cenyb	1.4733	
+kload_wenyb	1.2670	
+kload_ayb	1.2581	
+kload_qa	0.4461	
+kload_soa	1.2646	
+kload_sob	1.3026	
+# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	0.5528	
+tcyca_ema1	0.5525	
+tcyca_ema2	0.5518	
+tcyca_ema3	0.5517	
+tcyca_ema4	0.5912	
+tcyca_ema5	0.6193	
+tcyca_ema6	0.6546	
+tcyca_ema7	0.6826	
+tcycb_ema0	0.5623	
+tcycb_ema1	0.5654	
+tcycb_ema2	0.5675	
+tcycb_ema3	0.5718	
+tcycb_ema4	0.6191	
+tcycb_ema5	0.6469	
+tcycb_ema6	0.6893	
+tcycb_ema7	0.7174	
+# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.3927	
+tcracwb_rd1	0.3924	
+tcracwb_rd2	0.3917	
+tcracwb_rd3	0.3916	
+tcracwb_rd4	0.4311	
+tcracwb_rd5	0.4592	
+tcracwb_rd6	0.4944	
+tcracwb_rd7	0.5224	
+tcwbcra_wr0	0.4695	
+tcwbcra_wr1	0.4726	
+tcwbcra_wr2	0.4747	
+tcwbcra_wr3	0.4790	
+tcwbcra_wr4	0.5262	
+tcwbcra_wr5	0.5540	
+tcwbcra_wr6	0.5964	
+tcwbcra_wr7	0.6244	
+# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.0899	
+tckal	0.0871	
+tckbh	0.0886	
+tckbl	0.0843	
+# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.0849	
+taas	0.0866	
+taas_colldisn0	0.0866	
+tcenbs	0.0917	
+twenbs	0.0082	
+tabs	0.0910	
+tabs_colldisn0	0.0910	
+tdbs	0.0283	
+temaas	0.5758	
+temasas	0.5758	
+temabs	0.5958	
+ttenas	0.1554	
+ttcenas	0.0849	
+ttaas	0.0880	
+ttaas_colldisn0	0.0880	
+ttenbs	0.3531	
+ttcenbs	0.0930	
+ttwenbs	0.0084	
+ttabs	0.0924	
+ttabs_colldisn0	0.0924	
+ttdbs	0.0283	
+tsias	0.1710	
+tseas	0.1710	
+tdftrambypas	0.2057	
+tdftrambypbs	0.2057	
+tsibs	0.0283	
+tsebs	0.3531	
+tcolldisnas	0.5758	
+tcolldisnbs	0.5958	
+# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0376	
+tcenaf_ret1nfh	0.5948	
+tcenaf_ret1nrh	0.2791	
+taah	0.0643	
+taah_colldisn0	0.0643	
+tcenbh	0.0340	
+tcenbf_ret1nfh	0.5948	
+tcenbf_ret1nrh	0.2791	
+twenbh	0.1564	
+tabh	0.0531	
+tabh_colldisn0	0.0531	
+tdbh	0.1602	
+temaah	0.7560	
+temasah	0.7560	
+temabh	0.7403	
+ttenah	0.0707	
+ttcenah	0.0378	
+ttcenaf_ret1nfh	0.5948	
+ttcenaf_ret1nrh	0.2791	
+ttaah	0.0643	
+ttaah_colldisn0	0.0643	
+ttenbh	0.1766	
+ttcenbh	0.0340	
+ttcenbf_ret1nfh	0.5948	
+ttcenbf_ret1nrh	0.2791	
+ttwenbh	0.1569	
+ttabh	0.0531	
+ttabh_colldisn0	0.0531	
+ttdbh	0.1605	
+tret1nf_dftrambypfh	0.0232	
+tret1nr_dftrambypfh	0.5948	
+tret1nf_cenbrh	0.0232	
+tret1nf_cenarh	0.0212	
+tret1nf_tcenarh	0.0212	
+tret1nf_tcenbrh	0.0232	
+tret1nr_tcenbrh	0.5948	
+tret1nr_tcenarh	0.5747	
+tret1nr_cenbrh	0.5948	
+tret1nr_cenarh	0.5747	
+tsiah	0.0543	
+tseah	0.7560	
+tdftrambypah	0.7560	
+tdftrambypbh	0.5948	
+tdftrambypr_ret1nfh	0.5948	
+tdftrambypr_ret1nrh	0.2791	
+tsibh	0.1602	
+tsebh	0.1766	
+tcolldisnah	0.7560	
+tcolldisnbh	0.7403	
+# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0076	
+icap_cena	0.0012	
+icap_aa	0.0012	
+icap_clkb	0.0076	
+icap_cenb	0.0013	
+icap_wenb	0.0014	
+icap_ab	0.0012	
+icap_db	0.0015	
+icap_emaa	0.0044	
+icap_emasa	0.0018	
+icap_emab	0.0043	
+icap_tena	0.0009	
+icap_tcena	0.0012	
+icap_taa	0.0012	
+icap_tenb	0.0009	
+icap_tcenb	0.0014	
+icap_twenb	0.0012	
+icap_tab	0.0012	
+icap_tdb	0.0013	
+icap_sia	0.0011	
+icap_sea	0.0015	
+icap_dftrambyp	0.0017	
+icap_sib	0.0041	
+icap_seb	0.0015	
+icap_colldisn	0.0018	
+icap_ret1n	0.0028	
+# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	2.292e-03	
+icc_standby_p_chipdisable	9.632e-03	
+icc_standby_c_selective_precharge	2.277e-03	
+icc_standby_p_selective_precharge	8.341e-03	
+icc_standby_c_ret1	2.260e-03	
+icc_standby_p_ret1	8.341e-04	
+icc_c_rd0_a	9.165e-05	
+icc_c_rd1_a	9.165e-05	
+icc_c_rd2_a	9.165e-05	
+icc_c_rd3_a	9.165e-05	
+icc_c_rd4_a	9.432e-05	
+icc_c_rd5_a	9.585e-05	
+icc_c_rd6_a	9.741e-05	
+icc_c_rd7_a	9.814e-05	
+icc_p_rd0_a	3.597e-03	
+icc_p_rd1_a	3.597e-03	
+icc_p_rd2_a	3.597e-03	
+icc_p_rd3_a	3.597e-03	
+icc_p_rd4_a	3.605e-03	
+icc_p_rd5_a	3.609e-03	
+icc_p_rd6_a	3.613e-03	
+icc_p_rd7_a	3.616e-03	
+icc_c_wr0_b	2.175e-04	
+icc_c_wr1_b	2.175e-04	
+icc_c_wr2_b	2.175e-04	
+icc_c_wr3_b	2.175e-04	
+icc_c_wr4_b	2.202e-04	
+icc_c_wr5_b	2.218e-04	
+icc_c_wr6_b	2.233e-04	
+icc_c_wr7_b	2.241e-04	
+icc_p_wr0_b	4.929e-03	
+icc_p_wr1_b	4.929e-03	
+icc_p_wr2_b	4.929e-03	
+icc_p_wr3_b	4.929e-03	
+icc_p_wr4_b	4.933e-03	
+icc_p_wr5_b	4.938e-03	
+icc_p_wr6_b	4.941e-03	
+icc_p_wr7_b	4.944e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	6.445e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	1.157e-03	
+icc_c_peak	5.755785	
+icc_p_peak	75.373305	
+icc_c_inrush	2.053631	
+icc_p_inrush	40.179487	

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v

@@ -0,0 +1,275 @@
+/* verilog_rtl_memcomp Version: c0.1.0-EAC */
+/* common_memcomp Version: c0.1.2-EAC */
+/* lang compiler Version: 4.5.1-EAC Nov  6 2014 16:10:45 */
+//
+//       CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+//      
+//       Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+//      
+//       Use of this Software is subject to the terms and conditions of the
+//       applicable license agreement with ARM Physical IP, Inc.
+//       In addition, this Software is protected by patents, copyright law 
+//       and international treaties.
+//      
+//       The copyright notice(s) in this Software does not indicate actual or
+//       intended publication of this Software.
+//
+//       Repair Verilog RTL for High Capacity Two Port Register File SVT MVT Compiler
+//
+//       Instance Name:              rf2_32x128_wm1_rtl_top
+//       Words:                      32
+//       User Bits:                  128
+//       Mux:                        2
+//       Drive:                      6
+//       Write Mask:                 On
+//       Extra Margin Adjustment:    On
+//       Redundancy:                 off
+//       Redundant Rows:             0
+//       Redundant Columns:          2
+//       Test Muxes                  On
+//       Ser:                        none
+//       Retention:                  on
+//       Power Gating:               off
+//
+//       Creation Date:  Mon Oct 14 17:01:45 2019
+//       Version:      r0p0
+//
+//       Verified
+//
+//       Known Bugs: None.
+//
+//       Known Work Arounds: N/A
+//
+`timescale 1ns/1ps
+
+module rf2_32x128_wm1_rtl_top (
+          CENYA, 
+          AYA, 
+          CENYB, 
+          WENYB, 
+          AYB, 
+          QA, 
+          SOA, 
+          SOB, 
+          CLKA, 
+          CENA, 
+          AA, 
+          CLKB, 
+          CENB, 
+          WENB, 
+          AB, 
+          DB, 
+          EMAA, 
+          EMASA, 
+          EMAB, 
+          TENA, 
+          TCENA, 
+          TAA, 
+          TENB, 
+          TCENB, 
+          TWENB, 
+          TAB, 
+          TDB, 
+          RET1N, 
+          SIA, 
+          SEA, 
+          DFTRAMBYP, 
+          SIB, 
+          SEB, 
+          COLLDISN
+   );
+
+   output                   CENYA;
+   output [4:0]             AYA;
+   output                   CENYB;
+   output [127:0]           WENYB;
+   output [4:0]             AYB;
+   output [127:0]           QA;
+   output [1:0]             SOA;
+   output [1:0]             SOB;
+   input                    CLKA;
+   input                    CENA;
+   input [4:0]              AA;
+   input                    CLKB;
+   input                    CENB;
+   input [127:0]            WENB;
+   input [4:0]              AB;
+   input [127:0]            DB;
+   input [2:0]              EMAA;
+   input                    EMASA;
+   input [2:0]              EMAB;
+   input                    TENA;
+   input                    TCENA;
+   input [4:0]              TAA;
+   input                    TENB;
+   input                    TCENB;
+   input [127:0]            TWENB;
+   input [4:0]              TAB;
+   input [127:0]            TDB;
+   input                    RET1N;
+   input [1:0]              SIA;
+   input                    SEA;
+   input                    DFTRAMBYP;
+   input [1:0]              SIB;
+   input                    SEB;
+   input                    COLLDISN;
+   wire [127:0]             QOA;
+   wire [127:0]             DIB;
+
+   assign QA = QOA;
+   assign DIB = DB;
+   rf2_32x128_wm1_fr_top u0 (
+         .CENYA(CENYA),
+         .AYA(AYA),
+         .CENYB(CENYB),
+         .WENYB(WENYB),
+         .AYB(AYB),
+         .QOA(QOA),
+         .SOA(SOA),
+         .SOB(SOB),
+         .CLKA(CLKA),
+         .CENA(CENA),
+         .AA(AA),
+         .CLKB(CLKB),
+         .CENB(CENB),
+         .WENB(WENB),
+         .AB(AB),
+         .DIB(DIB),
+         .EMAA(EMAA),
+         .EMASA(EMASA),
+         .EMAB(EMAB),
+         .TENA(TENA),
+         .TCENA(TCENA),
+         .TAA(TAA),
+         .TENB(TENB),
+         .TCENB(TCENB),
+         .TWENB(TWENB),
+         .TAB(TAB),
+         .TDB(TDB),
+         .RET1N(RET1N),
+         .SIA(SIA),
+         .SEA(SEA),
+         .DFTRAMBYP(DFTRAMBYP),
+         .SIB(SIB),
+         .SEB(SEB),
+         .COLLDISN(COLLDISN)
+);
+
+endmodule
+
+module rf2_32x128_wm1_fr_top (
+          CENYA, 
+          AYA, 
+          CENYB, 
+          WENYB, 
+          AYB, 
+          QOA, 
+          SOA, 
+          SOB, 
+          CLKA, 
+          CENA, 
+          AA, 
+          CLKB, 
+          CENB, 
+          WENB, 
+          AB, 
+          DIB, 
+          EMAA, 
+          EMASA, 
+          EMAB, 
+          TENA, 
+          TCENA, 
+          TAA, 
+          TENB, 
+          TCENB, 
+          TWENB, 
+          TAB, 
+          TDB, 
+          RET1N, 
+          SIA, 
+          SEA, 
+          DFTRAMBYP, 
+          SIB, 
+          SEB, 
+          COLLDISN
+   );
+
+   output                   CENYA;
+   output [4:0]             AYA;
+   output                   CENYB;
+   output [127:0]           WENYB;
+   output [4:0]             AYB;
+   output [127:0]           QOA;
+   output [1:0]             SOA;
+   output [1:0]             SOB;
+   input                    CLKA;
+   input                    CENA;
+   input [4:0]              AA;
+   input                    CLKB;
+   input                    CENB;
+   input [127:0]            WENB;
+   input [4:0]              AB;
+   input [127:0]            DIB;
+   input [2:0]              EMAA;
+   input                    EMASA;
+   input [2:0]              EMAB;
+   input                    TENA;
+   input                    TCENA;
+   input [4:0]              TAA;
+   input                    TENB;
+   input                    TCENB;
+   input [127:0]            TWENB;
+   input [4:0]              TAB;
+   input [127:0]            TDB;
+   input                    RET1N;
+   input [1:0]              SIA;
+   input                    SEA;
+   input                    DFTRAMBYP;
+   input [1:0]              SIB;
+   input                    SEB;
+   input                    COLLDISN;
+
+   wire [127:0]    DB;
+   wire [127:0]    QA;
+
+   assign DB=DIB;
+   assign QOA=QA;
+   rf2_32x128_wm1 u0 (
+         .CENYA(CENYA),
+         .AYA(AYA),
+         .CENYB(CENYB),
+         .WENYB(WENYB),
+         .AYB(AYB),
+         .QA(QA),
+         .SOA(SOA),
+         .SOB(SOB),
+         .CLKA(CLKA),
+         .CENA(CENA),
+         .AA(AA),
+         .CLKB(CLKB),
+         .CENB(CENB),
+         .WENB(WENB),
+         .AB(AB),
+         .DB(DB),
+         .EMAA(EMAA),
+         .EMASA(EMASA),
+         .EMAB(EMAB),
+         .TENA(TENA),
+         .TCENA(TCENA),
+         .TAA(TAA),
+         .TENB(TENB),
+         .TCENB(TCENB),
+         .TWENB(TWENB),
+         .TAB(TAB),
+         .TDB(TDB),
+         .RET1N(RET1N),
+         .SIA(SIA),
+         .SEA(SEA),
+         .DFTRAMBYP(DFTRAMBYP),
+         .SIB(SIB),
+         .SEB(SEB),
+         .COLLDISN(COLLDISN)
+   );
+
+endmodule // rf2_32x128_wm1_fr_top
+

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:16 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     avm
+#   AMCI Version:                  2.0.4-EAC
+#   avm_memcomp Version:       2.3.7-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_32x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 4506
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS SS, CORNER SS_0P81V_0P81V_125C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.81 0.81
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 5.71087e-05nF
+    VDDPE VSSE 6.28090e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 0.85138mA
+    VDDPE VSSE 3.68611mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 6.28195e-05nF
+    VDDPE VSSE 5.76153e-03nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 0.93652mA
+    VDDPE VSSE 23.15579mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 2.89952e-04nF
+    VDDPE VSSE 8.92025e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 2.22663mA
+    VDDPE VSSE 24.23907mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 1.06570e-04nF
+    VDDPE VSSE 3.74491e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 1.06930mA
+    VDDPE VSSE 12.67500mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 1.83382e-04nF
+    VDDPE VSSE 5.17534e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 1.19590mA
+    VDDPE VSSE 16.68900mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 9.83176e-06nF
+    VDDPE VSSE 1.13987e-02nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.19692mA
+    VDDPE VSSE 16.41292mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 9.83176e-06nF
+    VDDPE VSSE 1.13987e-02nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.19692mA
+    VDDPE VSSE 16.41292mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 2.47655e-06nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 2.25737e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 1.39840e-02mA
+    VDDPE VSSE 0.11891mA
+  }
+  tsu 0.184945ns
+  ck2q_delay 0.724564ns
+  tr_q 0.036986ns
+  tf_q 0.041705ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat

@@ -0,0 +1,342 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:43 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     datatable
+#   AMCI Version:                  2.0.4-EAC
+#   datatable_memcomp Version:       2.3.2-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	ss_0p81v_0p81v_125c
+S	N
+geomx     	21.9750   
+geomy     	414.8600  
+volt      	0.8100    
+temp      	125.0000  
+# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.1698	
+ttcenacenya	0.1694	
+ttenacenyapu	0.2569	
+ttenacenyanu	0.3113	
+tdftrambypcenya	0.3774	
+taaaya	0.1761	
+ttaaaya	0.1785	
+ttenaayapu	0.3543	
+ttenaayanu	0.3264	
+tdftrambypaya	0.3634	
+tcenbcenyb	0.1739	
+ttcenbcenyb	0.1753	
+ttenbcenybpu	0.2627	
+ttenbcenybnu	0.4940	
+tdftrambypcenyb	0.3766	
+twenbwenyb	0.2544	
+ttwenbwenyb	0.2549	
+ttenbwenybpu	0.6549	
+ttenbwenybnu	0.6651	
+tdftrambypwenyb	0.3809	
+tabayb	0.1767	
+ttabayb	0.1803	
+ttenbaybpu	0.5579	
+ttenbaybnu	0.5197	
+tdftrambypayb	0.3592	
+taccqa_rd0	0.7072	
+taccqa_rd1	0.7115	
+taccqa_rd2	0.7168	
+taccqa_rd3	0.7246	
+taccqa_rd4	0.8255	
+taccqa_rd5	0.9233	
+taccqa_rd6	1.0320	
+taccqa_rd7	1.1298	
+taccqa_scan0	0.7072	
+taccqa_scan1	0.7115	
+taccqa_scan2	0.7168	
+taccqa_scan3	0.7246	
+taccqa_scan4	0.8255	
+taccqa_scan5	0.9233	
+taccqa_scan6	1.0320	
+taccqa_scan7	1.1298	
+tclkasoa_rd0	0.7968	
+tclkasoa_rd1	0.8011	
+tclkasoa_rd2	0.8064	
+tclkasoa_rd3	0.8142	
+tclkasoa_rd4	0.9152	
+tclkasoa_rd5	1.0130	
+tclkasoa_rd6	1.1217	
+tclkasoa_rd7	1.2196	
+tclkasoa_scan0	0.7968	
+tclkasoa_scan1	0.8011	
+tclkasoa_scan2	0.8064	
+tclkasoa_scan3	0.8142	
+tclkasoa_scan4	0.9152	
+tclkasoa_scan5	1.0130	
+tclkasoa_scan6	1.1217	
+tclkasoa_scan7	1.2196	
+tclkbsob	0.4309	
+# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	2.9544	
+kload_aya	2.6289	
+kload_cenyb	2.9646	
+kload_wenyb	2.6826	
+kload_ayb	2.6397	
+kload_qa	1.0456	
+kload_soa	2.6921	
+kload_sob	3.0759	
+# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	1.1173	
+tcyca_ema1	1.1218	
+tcyca_ema2	1.1273	
+tcyca_ema3	1.1354	
+tcyca_ema4	1.2406	
+tcyca_ema5	1.3425	
+tcyca_ema6	1.4559	
+tcyca_ema7	1.5578	
+tcycb_ema0	1.1869	
+tcycb_ema1	1.1955	
+tcycb_ema2	1.2067	
+tcycb_ema3	1.2169	
+tcycb_ema4	1.3370	
+tcycb_ema5	1.4353	
+tcycb_ema6	1.5677	
+tcycb_ema7	1.6682	
+# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.5452	
+tcracwb_rd1	0.5495	
+tcracwb_rd2	0.5548	
+tcracwb_rd3	0.5626	
+tcracwb_rd4	0.6635	
+tcracwb_rd5	0.7613	
+tcracwb_rd6	0.8700	
+tcracwb_rd7	0.9678	
+tcwbcra_wr0	0.8066	
+tcwbcra_wr1	0.8148	
+tcwbcra_wr2	0.8255	
+tcwbcra_wr3	0.8354	
+tcwbcra_wr4	0.9505	
+tcwbcra_wr5	1.0448	
+tcwbcra_wr6	1.1719	
+tcwbcra_wr7	1.2683	
+# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.1610	
+tckal	0.1731	
+tckbh	0.1602	
+tckbl	0.1727	
+# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.1727	
+taas	0.2271	
+taas_colldisn0	0.2271	
+tcenbs	0.1749	
+twenbs	0.0805	
+tabs	0.2247	
+tabs_colldisn0	0.2247	
+tdbs	0.1565	
+temaas	1.1981	
+temasas	1.1981	
+temabs	1.2797	
+ttenas	0.4007	
+ttcenas	0.1727	
+ttaas	0.2293	
+ttaas_colldisn0	0.2293	
+ttenbs	0.6900	
+ttcenbs	0.1755	
+ttwenbs	0.0805	
+ttabs	0.2278	
+ttabs_colldisn0	0.2278	
+ttdbs	0.1621	
+tsias	0.4408	
+tseas	0.4408	
+tdftrambypas	0.6586	
+tdftrambypbs	0.6586	
+tsibs	0.1565	
+tsebs	0.6900	
+tcolldisnas	1.1981	
+tcolldisnbs	1.2797	
+# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0677	
+tcenaf_ret1nfh	1.2585	
+tcenaf_ret1nrh	0.6220	
+taah	0.1038	
+taah_colldisn0	0.1038	
+tcenbh	0.0682	
+tcenbf_ret1nfh	1.2585	
+tcenbf_ret1nrh	0.6220	
+twenbh	0.2401	
+tabh	0.0966	
+tabh_colldisn0	0.0966	
+tdbh	0.2434	
+temaah	1.7699	
+temasah	1.7699	
+temabh	1.7098	
+ttenah	0.1142	
+ttcenah	0.0698	
+ttcenaf_ret1nfh	1.2585	
+ttcenaf_ret1nrh	0.6220	
+ttaah	0.1038	
+ttaah_colldisn0	0.1038	
+ttenbh	0.2678	
+ttcenbh	0.0682	
+ttcenbf_ret1nfh	1.2585	
+ttcenbf_ret1nrh	0.6220	
+ttwenbh	0.2417	
+ttabh	0.0966	
+ttabh_colldisn0	0.0966	
+ttdbh	0.2434	
+tret1nf_dftrambypfh	0.0439	
+tret1nr_dftrambypfh	1.2585	
+tret1nf_cenbrh	0.0439	
+tret1nf_cenarh	0.0432	
+tret1nf_tcenarh	0.0432	
+tret1nf_tcenbrh	0.0439	
+tret1nr_tcenbrh	1.2585	
+tret1nr_tcenarh	1.1769	
+tret1nr_cenbrh	1.2585	
+tret1nr_cenarh	1.1769	
+tsiah	0.0676	
+tseah	1.7699	
+tdftrambypah	1.7699	
+tdftrambypbh	1.2585	
+tdftrambypr_ret1nfh	1.2585	
+tdftrambypr_ret1nrh	0.6220	
+tsibh	0.2434	
+tsebh	0.2678	
+tcolldisnah	1.7699	
+tcolldisnbh	1.7098	
+# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0102	
+icap_cena	0.0019	
+icap_aa	0.0019	
+icap_clkb	0.0102	
+icap_cenb	0.0018	
+icap_wenb	0.0024	
+icap_ab	0.0020	
+icap_db	0.0024	
+icap_emaa	0.0075	
+icap_emasa	0.0030	
+icap_emab	0.0072	
+icap_tena	0.0013	
+icap_tcena	0.0019	
+icap_taa	0.0018	
+icap_tenb	0.0014	
+icap_tcenb	0.0019	
+icap_twenb	0.0020	
+icap_tab	0.0018	
+icap_tdb	0.0021	
+icap_sia	0.0018	
+icap_sea	0.0023	
+icap_dftrambyp	0.0024	
+icap_sib	0.0072	
+icap_seb	0.0022	
+icap_colldisn	0.0031	
+icap_ret1n	0.0045	
+# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	0.013984	
+icc_standby_p_chipdisable	0.118912	
+icc_standby_c_selective_precharge	0.013711	
+icc_standby_p_selective_precharge	0.101339	
+icc_standby_c_ret1	0.013252	
+icc_standby_p_ret1	0.010134	
+icc_c_rd0_a	8.583e-05	
+icc_c_rd1_a	8.592e-05	
+icc_c_rd2_a	8.598e-05	
+icc_c_rd3_a	8.632e-05	
+icc_c_rd4_a	8.821e-05	
+icc_c_rd5_a	8.914e-05	
+icc_c_rd6_a	8.941e-05	
+icc_c_rd7_a	8.941e-05	
+icc_p_rd0_a	3.026e-03	
+icc_p_rd1_a	3.026e-03	
+icc_p_rd2_a	3.030e-03	
+icc_p_rd3_a	3.033e-03	
+icc_p_rd4_a	3.068e-03	
+icc_p_rd5_a	3.073e-03	
+icc_p_rd6_a	3.081e-03	
+icc_p_rd7_a	3.081e-03	
+icc_c_wr0_b	1.479e-04	
+icc_c_wr1_b	1.480e-04	
+icc_c_wr2_b	1.483e-04	
+icc_c_wr3_b	1.485e-04	
+icc_c_wr4_b	1.504e-04	
+icc_c_wr5_b	1.514e-04	
+icc_c_wr6_b	1.517e-04	
+icc_c_wr7_b	1.517e-04	
+icc_p_wr0_b	4.185e-03	
+icc_p_wr1_b	4.185e-03	
+icc_p_wr2_b	4.189e-03	
+icc_p_wr3_b	4.192e-03	
+icc_p_wr4_b	4.226e-03	
+icc_p_wr5_b	4.232e-03	
+icc_p_wr6_b	4.239e-03	
+icc_p_wr7_b	4.239e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	4.035e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	9.960e-04	
+icc_c_peak	2.22663	
+icc_p_peak	24.239074	
+icc_c_inrush	1.225138	
+icc_p_inrush	23.084833	

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:25 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     avm
+#   AMCI Version:                  2.0.4-EAC
+#   avm_memcomp Version:       2.3.7-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_32x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 4506
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS TT, CORNER TT_0P81V_0P81V_0C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.81 0.81
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 5.49122e-05nF
+    VDDPE VSSE 6.03933e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 0.99817mA
+    VDDPE VSSE 4.32165mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 6.04034e-05nF
+    VDDPE VSSE 5.53994e-03nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 1.09799mA
+    VDDPE VSSE 27.14816mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 2.78800e-04nF
+    VDDPE VSSE 8.57721e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 2.22663mA
+    VDDPE VSSE 28.41823mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 1.02471e-04nF
+    VDDPE VSSE 3.60089e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 1.06930mA
+    VDDPE VSSE 12.67500mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 1.76329e-04nF
+    VDDPE VSSE 4.97632e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 1.19590mA
+    VDDPE VSSE 16.68900mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 9.45361e-06nF
+    VDDPE VSSE 1.09603e-02nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.18935mA
+    VDDPE VSSE 15.78165mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 9.45361e-06nF
+    VDDPE VSSE 1.09603e-02nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.18935mA
+    VDDPE VSSE 15.78165mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 2.47655e-06nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 2.17055e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 6.55600e-04mA
+    VDDPE VSSE 4.40600e-03mA
+  }
+  tsu 0.14063ns
+  ck2q_delay 0.664619ns
+  tr_q 0.020317ns
+  tf_q 0.023075ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat

@@ -0,0 +1,342 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Mon Oct 14 16:59:49 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_32x128_wm1
+#   Number of Words:               32
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            LL
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           on
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r0p0
+#   Lang compiler Version:         4.5.1-EAC
+#   View Name:                     datatable
+#   AMCI Version:                  2.0.4-EAC
+#   datatable_memcomp Version:       2.3.2-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	tt_0p81v_0p81v_0c
+S	N
+geomx     	21.9750   
+geomy     	414.8600  
+volt      	0.8100    
+temp      	0.0000    
+# High Capacity Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.1433	
+ttcenacenya	0.1430	
+ttenacenyapu	0.1952	
+ttenacenyanu	0.2353	
+tdftrambypcenya	0.2564	
+taaaya	0.1269	
+ttaaaya	0.1283	
+ttenaayapu	0.2365	
+ttenaayanu	0.2267	
+tdftrambypaya	0.2371	
+tcenbcenyb	0.1457	
+ttcenbcenyb	0.1462	
+ttenbcenybpu	0.2034	
+ttenbcenybnu	0.3394	
+tdftrambypcenyb	0.2475	
+twenbwenyb	0.1742	
+ttwenbwenyb	0.1735	
+ttenbwenybpu	0.4697	
+ttenbwenybnu	0.4927	
+tdftrambypwenyb	0.2830	
+tabayb	0.1276	
+ttabayb	0.1297	
+ttenbaybpu	0.3547	
+ttenbaybnu	0.3445	
+tdftrambypayb	0.2336	
+taccqa_rd0	0.6615	
+taccqa_rd1	0.6619	
+taccqa_rd2	0.6621	
+taccqa_rd3	0.6646	
+taccqa_rd4	0.7426	
+taccqa_rd5	0.8087	
+taccqa_rd6	0.8845	
+taccqa_rd7	0.9511	
+taccqa_scan0	0.6615	
+taccqa_scan1	0.6619	
+taccqa_scan2	0.6621	
+taccqa_scan3	0.6646	
+taccqa_scan4	0.7426	
+taccqa_scan5	0.8087	
+taccqa_scan6	0.8845	
+taccqa_scan7	0.9511	
+tclkasoa_rd0	0.7081	
+tclkasoa_rd1	0.7086	
+tclkasoa_rd2	0.7088	
+tclkasoa_rd3	0.7113	
+tclkasoa_rd4	0.7893	
+tclkasoa_rd5	0.8553	
+tclkasoa_rd6	0.9312	
+tclkasoa_rd7	0.9977	
+tclkasoa_scan0	0.7081	
+tclkasoa_scan1	0.7086	
+tclkasoa_scan2	0.7088	
+tclkasoa_scan3	0.7113	
+tclkasoa_scan4	0.7893	
+tclkasoa_scan5	0.8553	
+tclkasoa_scan6	0.9312	
+tclkasoa_scan7	0.9977	
+tclkbsob	0.3685	
+# High Capacity Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	2.6704	
+kload_aya	2.2063	
+kload_cenyb	2.6149	
+kload_wenyb	2.2794	
+kload_ayb	2.1961	
+kload_qa	0.8471	
+kload_soa	2.1164	
+kload_sob	2.2664	
+# High Capacity Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	0.9659	
+tcyca_ema1	0.9664	
+tcyca_ema2	0.9666	
+tcyca_ema3	0.9691	
+tcyca_ema4	1.0475	
+tcyca_ema5	1.1139	
+tcyca_ema6	1.1902	
+tcyca_ema7	1.2570	
+tcycb_ema0	0.9854	
+tcycb_ema1	0.9917	
+tcycb_ema2	0.9985	
+tcycb_ema3	1.0071	
+tcycb_ema4	1.0985	
+tcycb_ema5	1.1649	
+tcycb_ema6	1.2553	
+tcycb_ema7	1.3232	
+# High Capacity Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.5646	
+tcracwb_rd1	0.5651	
+tcracwb_rd2	0.5653	
+tcracwb_rd3	0.5678	
+tcracwb_rd4	0.6457	
+tcracwb_rd5	0.7116	
+tcracwb_rd6	0.7874	
+tcracwb_rd7	0.8538	
+tcwbcra_wr0	0.8095	
+tcwbcra_wr1	0.8158	
+tcwbcra_wr2	0.8225	
+tcwbcra_wr3	0.8311	
+tcwbcra_wr4	0.9219	
+tcwbcra_wr5	0.9878	
+tcwbcra_wr6	1.0776	
+tcwbcra_wr7	1.1450	
+# High Capacity Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.1491	
+tckal	0.1500	
+tckbh	0.1494	
+tckbl	0.1495	
+# High Capacity Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.1484	
+taas	0.1785	
+taas_colldisn0	0.1785	
+tcenbs	0.1506	
+twenbs	0.0379	
+tabs	0.1805	
+tabs_colldisn0	0.1805	
+tdbs	0.0998	
+temaas	1.0198	
+temasas	1.0198	
+temabs	1.0578	
+ttenas	0.3071	
+ttcenas	0.1484	
+ttaas	0.1798	
+ttaas_colldisn0	0.1798	
+ttenbs	0.6165	
+ttcenbs	0.1507	
+ttwenbs	0.0379	
+ttabs	0.1825	
+ttabs_colldisn0	0.1825	
+ttdbs	0.1050	
+tsias	0.3379	
+tseas	0.3379	
+tdftrambypas	0.4451	
+tdftrambypbs	0.4451	
+tsibs	0.0998	
+tsebs	0.6165	
+tcolldisnas	1.0198	
+tcolldisnbs	1.0578	
+# High Capacity Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0580	
+tcenaf_ret1nfh	1.0426	
+tcenaf_ret1nrh	0.5141	
+taah	0.0896	
+taah_colldisn0	0.0896	
+tcenbh	0.0589	
+tcenbf_ret1nfh	1.0426	
+tcenbf_ret1nrh	0.5141	
+twenbh	0.2220	
+tabh	0.0853	
+tabh_colldisn0	0.0853	
+tdbh	0.2104	
+temaah	1.4044	
+temasah	1.4044	
+temabh	1.3586	
+ttenah	0.0986	
+ttcenah	0.0588	
+ttcenaf_ret1nfh	1.0426	
+ttcenaf_ret1nrh	0.5141	
+ttaah	0.0896	
+ttaah_colldisn0	0.0896	
+ttenbh	0.2462	
+ttcenbh	0.0595	
+ttcenbf_ret1nfh	1.0426	
+ttcenbf_ret1nrh	0.5141	
+ttwenbh	0.2238	
+ttabh	0.0853	
+ttabh_colldisn0	0.0853	
+ttdbh	0.2104	
+tret1nf_dftrambypfh	0.0377	
+tret1nr_dftrambypfh	1.0426	
+tret1nf_cenbrh	0.0377	
+tret1nf_cenarh	0.0371	
+tret1nf_tcenarh	0.0371	
+tret1nf_tcenbrh	0.0377	
+tret1nr_tcenbrh	1.0426	
+tret1nr_tcenarh	1.0045	
+tret1nr_cenbrh	1.0426	
+tret1nr_cenarh	1.0045	
+tsiah	0.0946	
+tseah	1.4044	
+tdftrambypah	1.4044	
+tdftrambypbh	1.0426	
+tdftrambypr_ret1nfh	1.0426	
+tdftrambypr_ret1nrh	0.5141	
+tsibh	0.2104	
+tsebh	0.2462	
+tcolldisnah	1.4044	
+tcolldisnbh	1.3586	
+# High Capacity Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0093	
+icap_cena	0.0015	
+icap_aa	0.0016	
+icap_clkb	0.0093	
+icap_cenb	0.0016	
+icap_wenb	0.0019	
+icap_ab	0.0016	
+icap_db	0.0019	
+icap_emaa	0.0059	
+icap_emasa	0.0024	
+icap_emab	0.0057	
+icap_tena	0.0011	
+icap_tcena	0.0016	
+icap_taa	0.0015	
+icap_tenb	0.0011	
+icap_tcenb	0.0017	
+icap_twenb	0.0016	
+icap_tab	0.0016	
+icap_tdb	0.0017	
+icap_sia	0.0014	
+icap_sea	0.0018	
+icap_dftrambyp	0.0020	
+icap_sib	0.0054	
+icap_seb	0.0019	
+icap_colldisn	0.0024	
+icap_ret1n	0.0037	
+# High Capacity Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	6.556e-04	
+icc_standby_p_chipdisable	4.406e-03	
+icc_standby_c_selective_precharge	6.469e-04	
+icc_standby_p_selective_precharge	3.724e-03	
+icc_standby_c_ret1	6.357e-04	
+icc_standby_p_ret1	3.724e-04	
+icc_c_rd0_a	8.253e-05	
+icc_c_rd1_a	8.261e-05	
+icc_c_rd2_a	8.267e-05	
+icc_c_rd3_a	8.300e-05	
+icc_c_rd4_a	8.482e-05	
+icc_c_rd5_a	8.572e-05	
+icc_c_rd6_a	8.597e-05	
+icc_c_rd7_a	8.597e-05	
+icc_p_rd0_a	2.910e-03	
+icc_p_rd1_a	2.910e-03	
+icc_p_rd2_a	2.914e-03	
+icc_p_rd3_a	2.917e-03	
+icc_p_rd4_a	2.950e-03	
+icc_p_rd5_a	2.955e-03	
+icc_p_rd6_a	2.962e-03	
+icc_p_rd7_a	2.962e-03	
+icc_c_wr0_b	1.422e-04	
+icc_c_wr1_b	1.423e-04	
+icc_c_wr2_b	1.426e-04	
+icc_c_wr3_b	1.428e-04	
+icc_c_wr4_b	1.446e-04	
+icc_c_wr5_b	1.455e-04	
+icc_c_wr6_b	1.459e-04	
+icc_c_wr7_b	1.459e-04	
+icc_p_wr0_b	4.024e-03	
+icc_p_wr1_b	4.024e-03	
+icc_p_wr2_b	4.028e-03	
+icc_p_wr3_b	4.031e-03	
+icc_p_wr4_b	4.064e-03	
+icc_p_wr5_b	4.069e-03	
+icc_p_wr6_b	4.076e-03	
+icc_p_wr7_b	4.076e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	3.884e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	9.578e-04	
+icc_c_peak	2.22663	
+icc_p_peak	28.418225	
+icc_c_inrush	1.436369	
+icc_p_inrush	27.064976	

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp

@@ -0,0 +1,19 @@
+
+
+#include "Vrf2_32x128_wm1_rtl.h"
+#include "verilated.h"
+
+int main()
+{
+	Vrf2_32x128_wm1_rtl module;
+
+	for (int i = 0; i < 10; i++)
+	{
+		// module.clk = 0;
+    	module.eval();
+        // module.clk = 1;
+        module.eval();
+	}
+
+	return 0;
+}

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v

@@ -0,0 +1,87 @@
+`timescale 1ns/1ps
+
+
+module rf2_32x128_wm1_tb (
+	output [127 : 0] out_a_reg_data,
+	output reg clk,
+	output reg [4 : 0] rs1,
+	output reg [127 : 0] write_bit_mask,
+	output reg [4 : 0] rd,
+	output reg [127 : 0] write_data,
+	output reg cena,
+	output reg cenb
+);
+
+	initial begin
+		clk <= 1'b0;
+		rs1 <= 5'b0;
+		write_bit_mask <= {128{1'b1}};
+		rd <= 5'b0;
+		write_data <= 128'b0;
+		cena <= 1'b1;
+		cenb <= 1'b1;
+
+
+		
+		#100
+		cenb <= 1'b0;
+		write_bit_mask <= {{96{1'b1}}, {32{1'b0}}};
+		rd <= 5'h0a;
+		write_data <= 128'h0000_0002_0000_0002_0000_0002_0000_0002;
+		#10
+		cenb <= 1'b1;
+		write_bit_mask <= {128{1'b1}};
+		rd <= 5'b0;
+		write_data <= 128'b0;
+		
+		#100
+		cena <= 1'b0;
+		rs1 <= 5'h0a;
+
+
+
+	end
+
+	always @(clk) #5 clk <= ~clk;
+
+
+
+   rf2_32x128_wm1 first_ram (
+         .CENYA(),
+         .AYA(),
+         .CENYB(),
+         .WENYB(),
+         .AYB(),
+         .QA(out_a_reg_data),
+         .SOA(),
+         .SOB(),
+         .CLKA(clk),
+         .CENA(cena),
+         .AA(rs1),
+         .CLKB(clk),
+         .CENB(cenb),
+         .WENB(write_bit_mask),
+         .AB(rd),
+         .DB(write_data),
+         .EMAA(3'b011),
+         .EMASA(1'b0),
+         .EMAB(3'b011),
+         .TENA(1'b1),
+         .TCENA(1'b0),
+         .TAA(5'b0),
+         .TENB(1'b1),
+         .TCENB(1'b0),
+         .TWENB(128'b0),
+         .TAB(5'b0),
+         .TDB(128'b0),
+         .RET1N(1'b1),
+         .SIA(2'b0),
+         .SEA(1'b0),
+         .DFTRAMBYP(1'b0),
+         .SIB(2'b0),
+         .SEB(1'b0),
+         .COLLDISN(1'b1)
+   );
+
+endmodule 
+

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti

@@ -0,0 +1 @@
+

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript

@@ -0,0 +1,249 @@
+# //  ModelSim SE-64 10.6a Mar 16 2017Linux 3.10.0-1062.1.2.el7.x86_64
+# //
+# //  Copyright 1991-2017 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  ModelSim SE-64 and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading project rf_tb
+# Compile of rf2_32x128_wm1_tb.v was successful.
+vsim work.rf2_32x128_wm1_tb
+# vsim work.rf2_32x128_wm1_tb 
+# Start time: 19:36:40 on Oct 19,2019
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading work.rf2_32x128_wm1_tb(fast)
+# Loading work.rf2_32x128_wm1(fast)
+add wave -position insertpoint  \
+sim:/rf2_32x128_wm1_tb/out_a_reg_data \
+sim:/rf2_32x128_wm1_tb/clk \
+sim:/rf2_32x128_wm1_tb/rs1 \
+sim:/rf2_32x128_wm1_tb/write_bit_mask \
+sim:/rf2_32x128_wm1_tb/rd \
+sim:/rf2_32x128_wm1_tb/write_data \
+sim:/rf2_32x128_wm1_tb/cena \
+sim:/rf2_32x128_wm1_tb/cenb
+run
+run
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14065): $hold( posedge CLKB &&& RET1Neq1aTENBeq1:105 ns, negedge CENB:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14290): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[31]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14291): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[30]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14292): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[29]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14293): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[28]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14294): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[27]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14295): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[26]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14296): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[25]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14297): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[24]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14298): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[23]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14299): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[22]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14300): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[21]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14301): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[20]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14302): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[19]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14303): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[18]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14304): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[17]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14305): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[16]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14306): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[15]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14307): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[14]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14308): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[13]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14309): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[12]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14310): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[11]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14311): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[10]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14312): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[9]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14313): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[8]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14314): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[7]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14315): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[6]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14316): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[5]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14317): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[4]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14318): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[3]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14319): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[2]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14320): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[1]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14321): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[0]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14323): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, posedge AB[3]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14325): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, posedge AB[1]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14468): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aopopDFTRAMBYPeq1aSEBeq0cpoopDFTRAMBYPeq0aCENBeq0aWENB1eq0cpcp:105 ns, posedge DB[1]:105 ns, 500 ps );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14064): $hold( posedge CLKB &&& RET1Neq1aTENBeq1:115 ns, posedge CENB:115 ns, 500 ps );
+#    Time: 115 ns  Iteration: 2  Instance: /rf2_32x128_wm1_tb/first_ram
+run
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14043): $hold( posedge CLKA &&& RET1Neq1aTENAeq1:215 ns, negedge CENA:215 ns, 500 ps );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14045): $hold( posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, posedge AA[3]:215 ns, 500 ps );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14047): $hold( posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, posedge AA[1]:215 ns, 500 ps );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+# Causality operation skipped due to absence of debug database file
+quit -sim
+# End time: 19:44:22 on Oct 19,2019, Elapsed time: 0:07:42
+# Errors: 40, Warnings: 1
+# Compile of rf2_32x128_wm1_tb.v was successful.
+vsim work.rf2_32x128_wm1_tb
+# vsim work.rf2_32x128_wm1_tb 
+# Start time: 19:44:30 on Oct 19,2019
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading work.rf2_32x128_wm1_tb(fast)
+# Loading work.rf2_32x128_wm1(fast)
+add wave -position insertpoint  \
+sim:/rf2_32x128_wm1_tb/out_a_reg_data \
+sim:/rf2_32x128_wm1_tb/clk \
+sim:/rf2_32x128_wm1_tb/rs1 \
+sim:/rf2_32x128_wm1_tb/write_bit_mask \
+sim:/rf2_32x128_wm1_tb/rd \
+sim:/rf2_32x128_wm1_tb/write_data \
+sim:/rf2_32x128_wm1_tb/cena \
+sim:/rf2_32x128_wm1_tb/cenb
+run
+run
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14065): $setup( negedge CENB:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14290): $setup( negedge WENB[31]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14291): $setup( negedge WENB[30]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14292): $setup( negedge WENB[29]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14293): $setup( negedge WENB[28]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14294): $setup( negedge WENB[27]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14295): $setup( negedge WENB[26]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14296): $setup( negedge WENB[25]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14297): $setup( negedge WENB[24]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14298): $setup( negedge WENB[23]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14299): $setup( negedge WENB[22]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14300): $setup( negedge WENB[21]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14301): $setup( negedge WENB[20]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14302): $setup( negedge WENB[19]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14303): $setup( negedge WENB[18]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14304): $setup( negedge WENB[17]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14305): $setup( negedge WENB[16]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14306): $setup( negedge WENB[15]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14307): $setup( negedge WENB[14]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14308): $setup( negedge WENB[13]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14309): $setup( negedge WENB[12]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14310): $setup( negedge WENB[11]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14311): $setup( negedge WENB[10]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14312): $setup( negedge WENB[9]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14313): $setup( negedge WENB[8]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14314): $setup( negedge WENB[7]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14315): $setup( negedge WENB[6]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14316): $setup( negedge WENB[5]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14317): $setup( negedge WENB[4]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14318): $setup( negedge WENB[3]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14319): $setup( negedge WENB[2]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14320): $setup( negedge WENB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14321): $setup( negedge WENB[0]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14323): $setup( posedge AB[3]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14325): $setup( posedge AB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14468): $setup( posedge DB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aopopDFTRAMBYPeq1aSEBeq0cpoopDFTRAMBYPeq0aCENBeq0aWENB1eq0cpcp:105 ns, 1 ns );
+#    Time: 105 ns  Iteration: 5  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14064): $setup( posedge CENB:114500 ps, posedge CLKB &&& RET1Neq1aTENBeq1:115 ns, 1 ns );
+#    Time: 115 ns  Iteration: 2  Instance: /rf2_32x128_wm1_tb/first_ram
+run
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14043): $setup( negedge CENA:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1:215 ns, 1 ns );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14045): $setup( posedge AA[3]:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, 1 ns );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14047): $setup( posedge AA[1]:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, 1 ns );
+#    Time: 215 ns  Iteration: 3  Instance: /rf2_32x128_wm1_tb/first_ram
+quit -sim
+# End time: 19:45:39 on Oct 19,2019, Elapsed time: 0:01:09
+# Errors: 40, Warnings: 0
+vsim work.rf2_32x128_wm1_tb
+# vsim work.rf2_32x128_wm1_tb 
+# Start time: 19:45:52 on Oct 19,2019
+# ** Note: (vsim-8009) Loading existing optimized design _opt
+# Loading work.rf2_32x128_wm1_tb(fast)
+# Loading work.rf2_32x128_wm1(fast)
+quit -sim
+# End time: 19:46:00 on Oct 19,2019, Elapsed time: 0:00:08
+# Errors: 0, Warnings: 0
+# Compile of rf2_32x128_wm1_tb.v was successful.
+vsim work.rf2_32x128_wm1_tb
+# vsim work.rf2_32x128_wm1_tb 
+# Start time: 19:46:06 on Oct 19,2019
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading work.rf2_32x128_wm1_tb(fast)
+# Loading work.rf2_32x128_wm1(fast)
+add wave -position insertpoint  \
+sim:/rf2_32x128_wm1_tb/out_a_reg_data \
+sim:/rf2_32x128_wm1_tb/clk \
+sim:/rf2_32x128_wm1_tb/rs1 \
+sim:/rf2_32x128_wm1_tb/write_bit_mask \
+sim:/rf2_32x128_wm1_tb/rd \
+sim:/rf2_32x128_wm1_tb/write_data \
+sim:/rf2_32x128_wm1_tb/cena \
+sim:/rf2_32x128_wm1_tb/cenb
+run
+run
+run
+# End time: 12:47:27 on Oct 21,2019, Elapsed time: 41:01:21
+# Errors: 0, Warnings: 0

hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_info

@@ -0,0 +1,103 @@
+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+Z0 d/nethome/lzhu308/new_work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim
+T_opt
+!s110 1571528767
+V_7UfPa[jf=C_;A]OBZfl?1
+04 17 4 work rf2_32x128_wm1_tb fast 0
+=1-246e96c6651a-5daba03e-c1817-31ce
+o-quiet -auto_acc_if_foreign -work work
+Z1 tCvgOpt 0
+n@_opt
+OL;O;10.6a;65
+vdatapath_latch_rf2_32x128_wm1
+Z2 !s110 1571452808
+!i10b 1
+!s100 ]INaC9WCl@8^UmeThn]SW3
+IBVYhO=SVz2k6?d@Kom5ld2
+Z3 VDg1SIo80bB@j0V0VzS_@n1
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+Z6 F/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
+L0 59
+Z7 OL;L;10.6a;65
+r1
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+Z9 !s107 /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v|
+Z10 !s90 -reportprogress|300|-work|work|-vopt|-stats=none|/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v|
+!i113 0
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hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

hw/syn/synopsys/models/memory/cln28hpm/convertToDBAll.csh

@@ -0,0 +1,14 @@
+#! /bin/csh
+
+setenv SNPSLMD_LICENSE_FILE 1910@ece-winlic.ece.gatech.edu
+setenv PATH "${PATH}:/tools/synopsys/synthesis/j201409sp3/bin"
+setenv SYNOPSYS /tools/synopsys/synthesis/j201409sp3
+
+foreach ram (`ls`)
+	if ( -d ./$ram ) then
+		echo $ram
+		cd $ram
+		lc_shell -f ../convert_lib_to_db.tcl
+		cd ..
+	endif
+end

hw/syn/synopsys/models/memory/cln28hpm/convert_lib_to_db.tcl

@@ -0,0 +1,13 @@
+set SOURCE_FILES [glob *.lib]
+foreach FILE ${SOURCE_FILES} {
+    read_lib $FILE
+    redirect -variable CURR_LIB {get_lib}
+
+    set CURR_LIB [string range $CURR_LIB 2 end-3] 
+    set CURR_LIB [lindex  $CURR_LIB 0]
+    set FILENAME [string range $FILE 0 end-4]
+    write_lib $CURR_LIB -output ${FILENAME}.db
+    remove_lib $CURR_LIB
+}
+
+exit

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.memlib

@@ -0,0 +1,359 @@
+/* logicvision_memcomp Version: c0.1.2-beta */
+/* common_memcomp Version: c0.1.0-EAC */
+/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
+//
+//       CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+//      
+//       Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+//      
+//       Use of this Software is subject to the terms and conditions of the
+//       applicable license agreement with ARM Physical IP, Inc.
+//       In addition, this Software is protected by patents, copyright law 
+//       and international treaties.
+//      
+//       The copyright notice(s) in this Software does not indicate actual or
+//       intended publication of this Software.
+//
+//      logicvision model for High Density Two Port Register File SVT MVT Compiler
+//
+//      Instance Name:              rf2_128x128_wm1
+//      Words:                      128
+//      Bits:                       128
+//      Mux:                        2
+//      Drive:                      6
+//      Write Mask:                 On
+//      Extra Margin Adjustment:    On
+//      Redundant Rows:             0
+//      Redundant Columns:          2
+//      Test Muxes                  On
+//
+//      Creation Date:  Sun Oct 20 14:48:39 2019
+//      Version: 	r4p0
+//
+//      Modeling Assumptions: 
+//
+//      Modeling Limitations: None
+//
+//      Known Bugs: None.
+//
+//      Known Work Arounds: N/A
+//
+MemoryTemplate (rf2_128x128_wm1) {
+	Algorithm : SmarchChkbvcd;
+	DataOutStage : None;
+	LogicalPorts : 1R1W;
+	BitGrouping : 1;
+	MemoryType : SRAM;
+	MinHold : 0.5;
+	OperationSet : SyncWRvcd;
+	SelectDuringWriteThru : Off;
+	ShadowRead : On;
+	ShadowWrite : On;
+        TransparentMode : None;
+        ObservationLogic: On;
+        InternalScanLogic: On;
+	CellName : rf2_128x128_wm1;
+	NumberOfWords : 128;
+	AddressCounter{
+		Function (Address) {
+			LogicalAddressMap{
+				ColumnAddress[0] : Address[0];
+				RowAddress[5:0] : Address[6:1];
+			}
+		}
+		Function (ColumnAddress) {
+			CountRange [0:1];
+			}
+		Function (RowAddress) {
+			CountRange [0:63];
+		}
+	}
+	PhysicalAddressMap{
+		ColumnAddress[0] : c[0];
+		RowAddress[0] : r[0];
+		RowAddress[1] : r[1];
+		RowAddress[2] : r[2];
+		RowAddress[3] : r[3];
+		RowAddress[4] : r[4];
+		RowAddress[5] : r[5];
+	}
+	PhysicalDataMap{
+		Data[0] : NOT d[0];
+		Data[1] : NOT d[1];
+		Data[2] : NOT d[2];
+		Data[3] : NOT d[3];
+		Data[4] : NOT d[4];
+		Data[5] : NOT d[5];
+		Data[6] : NOT d[6];
+		Data[7] : NOT d[7];
+		Data[8] : NOT d[8];
+		Data[9] : NOT d[9];
+		Data[10] : NOT d[10];
+		Data[11] : NOT d[11];
+		Data[12] : NOT d[12];
+		Data[13] : NOT d[13];
+		Data[14] : NOT d[14];
+		Data[15] : NOT d[15];
+		Data[16] : NOT d[16];
+		Data[17] : NOT d[17];
+		Data[18] : NOT d[18];
+		Data[19] : NOT d[19];
+		Data[20] : NOT d[20];
+		Data[21] : NOT d[21];
+		Data[22] : NOT d[22];
+		Data[23] : NOT d[23];
+		Data[24] : NOT d[24];
+		Data[25] : NOT d[25];
+		Data[26] : NOT d[26];
+		Data[27] : NOT d[27];
+		Data[28] : NOT d[28];
+		Data[29] : NOT d[29];
+		Data[30] : NOT d[30];
+		Data[31] : NOT d[31];
+		Data[32] : NOT d[32];
+		Data[33] : NOT d[33];
+		Data[34] : NOT d[34];
+		Data[35] : NOT d[35];
+		Data[36] : NOT d[36];
+		Data[37] : NOT d[37];
+		Data[38] : NOT d[38];
+		Data[39] : NOT d[39];
+		Data[40] : NOT d[40];
+		Data[41] : NOT d[41];
+		Data[42] : NOT d[42];
+		Data[43] : NOT d[43];
+		Data[44] : NOT d[44];
+		Data[45] : NOT d[45];
+		Data[46] : NOT d[46];
+		Data[47] : NOT d[47];
+		Data[48] : NOT d[48];
+		Data[49] : NOT d[49];
+		Data[50] : NOT d[50];
+		Data[51] : NOT d[51];
+		Data[52] : NOT d[52];
+		Data[53] : NOT d[53];
+		Data[54] : NOT d[54];
+		Data[55] : NOT d[55];
+		Data[56] : NOT d[56];
+		Data[57] : NOT d[57];
+		Data[58] : NOT d[58];
+		Data[59] : NOT d[59];
+		Data[60] : NOT d[60];
+		Data[61] : NOT d[61];
+		Data[62] : NOT d[62];
+		Data[63] : NOT d[63];
+		Data[64] : d[64];
+		Data[65] : d[65];
+		Data[66] : d[66];
+		Data[67] : d[67];
+		Data[68] : d[68];
+		Data[69] : d[69];
+		Data[70] : d[70];
+		Data[71] : d[71];
+		Data[72] : d[72];
+		Data[73] : d[73];
+		Data[74] : d[74];
+		Data[75] : d[75];
+		Data[76] : d[76];
+		Data[77] : d[77];
+		Data[78] : d[78];
+		Data[79] : d[79];
+		Data[80] : d[80];
+		Data[81] : d[81];
+		Data[82] : d[82];
+		Data[83] : d[83];
+		Data[84] : d[84];
+		Data[85] : d[85];
+		Data[86] : d[86];
+		Data[87] : d[87];
+		Data[88] : d[88];
+		Data[89] : d[89];
+		Data[90] : d[90];
+		Data[91] : d[91];
+		Data[92] : d[92];
+		Data[93] : d[93];
+		Data[94] : d[94];
+		Data[95] : d[95];
+		Data[96] : d[96];
+		Data[97] : d[97];
+		Data[98] : d[98];
+		Data[99] : d[99];
+		Data[100] : d[100];
+		Data[101] : d[101];
+		Data[102] : d[102];
+		Data[103] : d[103];
+		Data[104] : d[104];
+		Data[105] : d[105];
+		Data[106] : d[106];
+		Data[107] : d[107];
+		Data[108] : d[108];
+		Data[109] : d[109];
+		Data[110] : d[110];
+		Data[111] : d[111];
+		Data[112] : d[112];
+		Data[113] : d[113];
+		Data[114] : d[114];
+		Data[115] : d[115];
+		Data[116] : d[116];
+		Data[117] : d[117];
+		Data[118] : d[118];
+		Data[119] : d[119];
+		Data[120] : d[120];
+		Data[121] : d[121];
+		Data[122] : d[122];
+		Data[123] : d[123];
+		Data[124] : d[124];
+		Data[125] : d[125];
+		Data[126] : d[126];
+		Data[127] : d[127];
+	}
+	Port (AA[6:0]) {
+		Function : Address;
+		LogicalPort : A;
+		EmbeddedTestLogic {
+			TestInput : TAA[6:0];
+			TestOutput : AYA[6:0];
+		}
+	}
+	Port (QA[127:0]) {
+		Function : Data;
+		Direction : output;
+		LogicalPort : A;
+	}
+	Port (CENA) {
+		Function : ReadEnable;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENA;
+			TestOutput : CENYA;
+		}
+	}
+	Port (TENA) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+	}
+	Port (CLKA) {
+		Function : Clock;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAA[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMASA) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+  port (SEA){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIA[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOA[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+  port (DFTRAMBYP){
+          Function : ScanTest;
+          Direction : Input;
+          Polarity : ActiveHigh;
+  }
+	Port (AB[6:0]) {
+		Function : Address;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TAB[6:0];
+			TestOutput : AYB[6:0];
+		}
+	}
+	Port (DB[127:0]) {
+		Function : Data;
+		Direction : input;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TDB[127:0];
+		}
+	}
+	Port (WENB[127:0]) {
+		Function : GroupWriteEnable;
+                BitsPerWriteEnable: 1;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TWENB[127:0];
+			TestOutput : WENYB[127:0];
+		}
+	}
+	Port (CENB) {
+		Function : WriteEnable;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENB;
+			TestOutput : CENYB;
+		}
+	}
+	Port (TENB) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+	}
+	Port (CLKB) {
+		Function : Clock;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAB[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (COLLDISN) {
+             Function : None;
+             SafeValue : 1;
+             Direction : Input;
+             Polarity : ActiveLow;
+       }
+  port (SEB){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIB[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOB[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+	port (RET1N){
+		Function : None;
+		Direction : Input;
+		SafeValue : 1;
+		Polarity : Activelow;
+	}
+}

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ff_0p99v_0p99v_125c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:45:53 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     avm
+#   AMCI Version:                  1.4.3-EAC
+#   avm_memcomp Version:       2.1.1-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_128x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 18022
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.99 0.99
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 1.02612e-04nF
+    VDDPE VSSE 6.12732e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 3.08056mA
+    VDDPE VSSE 8.89592mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 1.12874e-04nF
+    VDDPE VSSE 1.10761e-02nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 3.38862mA
+    VDDPE VSSE 96.55176mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 3.50286e-04nF
+    VDDPE VSSE 9.97299e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 8.09467mA
+    VDDPE VSSE 101.37935mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 1.00598e-04nF
+    VDDPE VSSE 4.46207e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 2.28932mA
+    VDDPE VSSE 60.92520mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 2.49688e-04nF
+    VDDPE VSSE 5.51093e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 5.32434mA
+    VDDPE VSSE 89.27310mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 8.09457e-06nF
+    VDDPE VSSE 1.07376e-02nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.43640mA
+    VDDPE VSSE 39.07064mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 8.09457e-06nF
+    VDDPE VSSE 1.07376e-02nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.43640mA
+    VDDPE VSSE 39.07064mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.95501e-05nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 2.17223e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 0.89726mA
+    VDDPE VSSE 1.79810mA
+  }
+  tsu 0.102996ns
+  ck2q_delay 0.553048ns
+  tr_q 0.013743ns
+  tf_q 0.015878ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ff_0p99v_0p99v_125c.dat

@@ -0,0 +1,334 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:46:18 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     datatable
+#   AMCI Version:                  1.4.3-EAC
+#   datatable_memcomp Version:       1.3.0-amci
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	ff_0p99v_0p99v_125c
+S	N
+geomx     	34.1250   
+geomy     	414.8600  
+volt      	0.9900    
+temp      	125.0000  
+# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.0917	
+ttcenacenya	0.0905	
+ttenacenyapu	0.1191	
+ttenacenyanu	0.1400	
+tdftrambypcenya	0.1299	
+taaaya	0.0751	
+ttaaaya	0.0751	
+ttenaayapu	0.1377	
+ttenaayanu	0.1338	
+tdftrambypaya	0.1197	
+tcenbcenyb	0.0947	
+ttcenbcenyb	0.0939	
+ttenbcenybpu	0.1236	
+ttenbcenybnu	0.1996	
+tdftrambypcenyb	0.1226	
+twenbwenyb	0.0927	
+ttwenbwenyb	0.0930	
+ttenbwenybpu	0.2539	
+ttenbwenybnu	0.2667	
+tdftrambypwenyb	0.1651	
+tabayb	0.0753	
+ttabayb	0.0779	
+ttenbaybpu	0.1929	
+ttenbaybnu	0.1969	
+tdftrambypayb	0.1194	
+taccqa_rd0	0.5372	
+taccqa_rd1	0.5462	
+taccqa_rd2	0.5490	
+taccqa_rd3	0.5530	
+taccqa_rd4	0.5979	
+taccqa_rd5	0.6317	
+taccqa_rd6	0.6718	
+taccqa_rd7	0.7078	
+taccqa_scan0	0.5372	
+taccqa_scan1	0.5462	
+taccqa_scan2	0.5490	
+taccqa_scan3	0.5530	
+taccqa_scan4	0.5979	
+taccqa_scan5	0.6317	
+taccqa_scan6	0.6718	
+taccqa_scan7	0.7078	
+tclkasoa_rd0	0.5506	
+tclkasoa_rd1	0.5596	
+tclkasoa_rd2	0.5624	
+tclkasoa_rd3	0.5665	
+tclkasoa_rd4	0.6114	
+tclkasoa_rd5	0.6452	
+tclkasoa_rd6	0.6853	
+tclkasoa_rd7	0.7213	
+tclkasoa_scan0	0.5506	
+tclkasoa_scan1	0.5596	
+tclkasoa_scan2	0.5624	
+tclkasoa_scan3	0.5665	
+tclkasoa_scan4	0.6114	
+tclkasoa_scan5	0.6452	
+tclkasoa_scan6	0.6853	
+tclkasoa_scan7	0.7213	
+tclkbsob	0.2290	
+# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	1.7116	
+kload_aya	1.4236	
+kload_cenyb	1.6712	
+kload_wenyb	1.4498	
+kload_ayb	1.4006	
+kload_qa	0.5053	
+kload_soa	1.3720	
+kload_sob	1.4400	
+# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	0.7585	
+tcyca_ema1	0.7676	
+tcyca_ema2	0.7705	
+tcyca_ema3	0.7746	
+tcyca_ema4	0.8201	
+tcyca_ema5	0.8545	
+tcyca_ema6	0.8951	
+tcyca_ema7	0.9317	
+tcycb_ema0	0.8745	
+tcycb_ema1	0.9245	
+tcycb_ema2	0.9393	
+tcycb_ema3	0.9716	
+tcycb_ema4	1.0232	
+tcycb_ema5	1.0589	
+tcycb_ema6	1.1078	
+tcycb_ema7	1.1429	
+# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.5419	
+tcracwb_rd1	0.5509	
+tcracwb_rd2	0.5537	
+tcracwb_rd3	0.5577	
+tcracwb_rd4	0.6026	
+tcracwb_rd5	0.6364	
+tcracwb_rd6	0.6765	
+tcracwb_rd7	0.7125	
+tcwbcra_wr0	0.6577	
+tcwbcra_wr1	0.7069	
+tcwbcra_wr2	0.7215	
+tcwbcra_wr3	0.7533	
+tcwbcra_wr4	0.8041	
+tcwbcra_wr5	0.8394	
+tcwbcra_wr6	0.8875	
+tcwbcra_wr7	0.9221	
+# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.0927	
+tckal	0.0899	
+tckbh	0.0959	
+tckbl	0.0907	
+# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.0902	
+taas	0.1030	
+tcenbs	0.0963	
+twenbs	0.0150	
+tabs	0.1100	
+tdbs	0.0228	
+temaas	0.7999	
+temasas	0.7999	
+temabs	0.9969	
+ttenas	0.1840	
+ttcenas	0.0905	
+ttaas	0.1051	
+ttenbs	0.3881	
+ttcenbs	0.0968	
+ttwenbs	0.0151	
+ttabs	0.1137	
+ttdbs	0.0237	
+tsias	0.2024	
+tseas	0.2024	
+tdftrambypas	0.2266	
+tdftrambypbs	0.2266	
+tsibs	0.0228	
+tsebs	0.3881	
+tcolldisnas	0.7999	
+tcolldisnbs	0.9969	
+# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0403	
+tcenaf_ret1nfh	1.0066	
+tcenaf_ret1nrh	0.3610	
+taah	0.0702	
+tcenbh	0.0423	
+tcenbf_ret1nfh	1.0066	
+tcenbf_ret1nrh	0.3610	
+twenbh	0.1736	
+tabh	0.0649	
+tdbh	0.1710	
+temaah	1.0210	
+temasah	1.0210	
+temabh	1.1778	
+ttenah	0.0772	
+ttcenah	0.0416	
+ttcenaf_ret1nfh	1.0066	
+ttcenaf_ret1nrh	0.3610	
+ttaah	0.0702	
+ttenbh	0.1918	
+ttcenbh	0.0436	
+ttcenbf_ret1nfh	1.0066	
+ttcenbf_ret1nrh	0.3610	
+ttwenbh	0.1743	
+ttabh	0.0649	
+ttdbh	0.1710	
+tret1nf_dftrambypfh	0.0242	
+tret1nr_dftrambypfh	1.0066	
+tret1nf_cenbrh	0.0242	
+tret1nf_cenarh	0.0226	
+tret1nf_tcenarh	0.0226	
+tret1nf_tcenbrh	0.0242	
+tret1nr_tcenbrh	1.0066	
+tret1nr_tcenarh	0.8096	
+tret1nr_cenbrh	1.0066	
+tret1nr_cenarh	0.8096	
+tsiah	0.0756	
+tseah	1.0210	
+tdftrambypah	1.0210	
+tdftrambypbh	1.0066	
+tdftrambypr_ret1nfh	1.0066	
+tdftrambypr_ret1nrh	0.3610	
+tsibh	0.1710	
+tsebh	0.1918	
+tcolldisnah	1.0210	
+tcolldisnbh	1.1778	
+# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0105	
+icap_cena	0.0018	
+icap_aa	0.0012	
+icap_clkb	0.0106	
+icap_cenb	0.0015	
+icap_wenb	0.0017	
+icap_ab	0.0012	
+icap_db	0.0019	
+icap_emaa	0.0059	
+icap_emasa	0.0021	
+icap_emab	0.0057	
+icap_tena	0.0010	
+icap_tcena	0.0016	
+icap_taa	0.0014	
+icap_tenb	0.0012	
+icap_tcenb	0.0016	
+icap_twenb	0.0015	
+icap_tab	0.0014	
+icap_tdb	0.0016	
+icap_sia	0.0015	
+icap_sea	0.0019	
+icap_dftrambyp	0.0021	
+icap_sib	0.0056	
+icap_seb	0.0019	
+icap_colldisn	0.0024	
+icap_ret1n	0.0035	
+# High Density Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	0.897263	
+icc_standby_p_chipdisable	1.798096	
+icc_standby_c_ret1	1.033638	
+icc_standby_p_ret1	0.183674	
+icc_standby_c_selective_precharge	0.880166	
+icc_standby_p_selective_precharge	1.478917	
+icc_c_rd0_a	9.867e-05	
+icc_c_rd1_a	9.873e-05	
+icc_c_rd2_a	9.948e-05	
+icc_c_rd3_a	9.959e-05	
+icc_c_rd4_a	1.012e-04	
+icc_c_rd5_a	1.022e-04	
+icc_c_rd6_a	1.039e-04	
+icc_c_rd7_a	1.052e-04	
+icc_p_rd0_a	4.364e-03	
+icc_p_rd1_a	4.405e-03	
+icc_p_rd2_a	4.405e-03	
+icc_p_rd3_a	4.417e-03	
+icc_p_rd4_a	4.533e-03	
+icc_p_rd5_a	4.575e-03	
+icc_p_rd6_a	4.604e-03	
+icc_p_rd7_a	4.616e-03	
+icc_c_wr0_b	2.463e-04	
+icc_c_wr1_b	2.463e-04	
+icc_c_wr2_b	2.471e-04	
+icc_c_wr3_b	2.472e-04	
+icc_c_wr4_b	2.488e-04	
+icc_c_wr5_b	2.498e-04	
+icc_c_wr6_b	2.515e-04	
+icc_c_wr7_b	2.528e-04	
+icc_p_wr0_b	5.403e-03	
+icc_p_wr1_b	5.444e-03	
+icc_p_wr2_b	5.444e-03	
+icc_p_wr3_b	5.456e-03	
+icc_p_wr4_b	5.572e-03	
+icc_p_wr5_b	5.613e-03	
+icc_p_wr6_b	5.643e-03	
+icc_p_wr7_b	5.655e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	8.252e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	1.180e-03	
+icc_c_peak	8.094665	
+icc_p_peak	101.379348	
+icc_c_inrush	3.629571	
+icc_p_inrush	96.55176	

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_rtl.v

@@ -0,0 +1,275 @@
+/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
+/* common_memcomp Version: 4.0.5.2-amci */
+/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
+//
+//       CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+//      
+//       Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+//      
+//       Use of this Software is subject to the terms and conditions of the
+//       applicable license agreement with ARM Physical IP, Inc.
+//       In addition, this Software is protected by patents, copyright law 
+//       and international treaties.
+//      
+//       The copyright notice(s) in this Software does not indicate actual or
+//       intended publication of this Software.
+//
+//       Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
+//
+//       Instance Name:              rf2_128x128_wm1_rtl_top
+//       Words:                      128
+//       User Bits:                  128
+//       Mux:                        2
+//       Drive:                      6
+//       Write Mask:                 On
+//       Extra Margin Adjustment:    On
+//       Redundancy:                 off
+//       Redundant Rows:             0
+//       Redundant Columns:          2
+//       Test Muxes                  On
+//       Ser:                        none
+//       Retention:                  on
+//       Power Gating:               off
+//
+//       Creation Date:  Sun Oct 20 14:49:15 2019
+//       Version:      r4p0
+//
+//       Verified
+//
+//       Known Bugs: None.
+//
+//       Known Work Arounds: N/A
+//
+`timescale 1ns/1ps
+
+module rf2_128x128_wm1_rtl_top (
+          CENYA, 
+          AYA, 
+          CENYB, 
+          WENYB, 
+          AYB, 
+          QA, 
+          SOA, 
+          SOB, 
+          CLKA, 
+          CENA, 
+          AA, 
+          CLKB, 
+          CENB, 
+          WENB, 
+          AB, 
+          DB, 
+          EMAA, 
+          EMASA, 
+          EMAB, 
+          TENA, 
+          TCENA, 
+          TAA, 
+          TENB, 
+          TCENB, 
+          TWENB, 
+          TAB, 
+          TDB, 
+          RET1N, 
+          SIA, 
+          SEA, 
+          DFTRAMBYP, 
+          SIB, 
+          SEB, 
+          COLLDISN
+   );
+
+   output                   CENYA;
+   output [6:0]             AYA;
+   output                   CENYB;
+   output [127:0]           WENYB;
+   output [6:0]             AYB;
+   output [127:0]           QA;
+   output [1:0]             SOA;
+   output [1:0]             SOB;
+   input                    CLKA;
+   input                    CENA;
+   input [6:0]              AA;
+   input                    CLKB;
+   input                    CENB;
+   input [127:0]            WENB;
+   input [6:0]              AB;
+   input [127:0]            DB;
+   input [2:0]              EMAA;
+   input                    EMASA;
+   input [2:0]              EMAB;
+   input                    TENA;
+   input                    TCENA;
+   input [6:0]              TAA;
+   input                    TENB;
+   input                    TCENB;
+   input [127:0]            TWENB;
+   input [6:0]              TAB;
+   input [127:0]            TDB;
+   input                    RET1N;
+   input [1:0]              SIA;
+   input                    SEA;
+   input                    DFTRAMBYP;
+   input [1:0]              SIB;
+   input                    SEB;
+   input                    COLLDISN;
+   wire [127:0]             QOA;
+   wire [127:0]             DIB;
+
+   assign QA = QOA;
+   assign DIB = DB;
+   rf2_128x128_wm1_fr_top u0 (
+         .CENYA(CENYA),
+         .AYA(AYA),
+         .CENYB(CENYB),
+         .WENYB(WENYB),
+         .AYB(AYB),
+         .QOA(QOA),
+         .SOA(SOA),
+         .SOB(SOB),
+         .CLKA(CLKA),
+         .CENA(CENA),
+         .AA(AA),
+         .CLKB(CLKB),
+         .CENB(CENB),
+         .WENB(WENB),
+         .AB(AB),
+         .DIB(DIB),
+         .EMAA(EMAA),
+         .EMASA(EMASA),
+         .EMAB(EMAB),
+         .TENA(TENA),
+         .TCENA(TCENA),
+         .TAA(TAA),
+         .TENB(TENB),
+         .TCENB(TCENB),
+         .TWENB(TWENB),
+         .TAB(TAB),
+         .TDB(TDB),
+         .RET1N(RET1N),
+         .SIA(SIA),
+         .SEA(SEA),
+         .DFTRAMBYP(DFTRAMBYP),
+         .SIB(SIB),
+         .SEB(SEB),
+         .COLLDISN(COLLDISN)
+);
+
+endmodule
+
+module rf2_128x128_wm1_fr_top (
+          CENYA, 
+          AYA, 
+          CENYB, 
+          WENYB, 
+          AYB, 
+          QOA, 
+          SOA, 
+          SOB, 
+          CLKA, 
+          CENA, 
+          AA, 
+          CLKB, 
+          CENB, 
+          WENB, 
+          AB, 
+          DIB, 
+          EMAA, 
+          EMASA, 
+          EMAB, 
+          TENA, 
+          TCENA, 
+          TAA, 
+          TENB, 
+          TCENB, 
+          TWENB, 
+          TAB, 
+          TDB, 
+          RET1N, 
+          SIA, 
+          SEA, 
+          DFTRAMBYP, 
+          SIB, 
+          SEB, 
+          COLLDISN
+   );
+
+   output                   CENYA;
+   output [6:0]             AYA;
+   output                   CENYB;
+   output [127:0]           WENYB;
+   output [6:0]             AYB;
+   output [127:0]           QOA;
+   output [1:0]             SOA;
+   output [1:0]             SOB;
+   input                    CLKA;
+   input                    CENA;
+   input [6:0]              AA;
+   input                    CLKB;
+   input                    CENB;
+   input [127:0]            WENB;
+   input [6:0]              AB;
+   input [127:0]            DIB;
+   input [2:0]              EMAA;
+   input                    EMASA;
+   input [2:0]              EMAB;
+   input                    TENA;
+   input                    TCENA;
+   input [6:0]              TAA;
+   input                    TENB;
+   input                    TCENB;
+   input [127:0]            TWENB;
+   input [6:0]              TAB;
+   input [127:0]            TDB;
+   input                    RET1N;
+   input [1:0]              SIA;
+   input                    SEA;
+   input                    DFTRAMBYP;
+   input [1:0]              SIB;
+   input                    SEB;
+   input                    COLLDISN;
+
+   wire [127:0]    DB;
+   wire [127:0]    QA;
+
+   assign DB=DIB;
+   assign QOA=QA;
+   rf2_128x128_wm1 u0 (
+         .CENYA(CENYA),
+         .AYA(AYA),
+         .CENYB(CENYB),
+         .WENYB(WENYB),
+         .AYB(AYB),
+         .QA(QA),
+         .SOA(SOA),
+         .SOB(SOB),
+         .CLKA(CLKA),
+         .CENA(CENA),
+         .AA(AA),
+         .CLKB(CLKB),
+         .CENB(CENB),
+         .WENB(WENB),
+         .AB(AB),
+         .DB(DB),
+         .EMAA(EMAA),
+         .EMASA(EMASA),
+         .EMAB(EMAB),
+         .TENA(TENA),
+         .TCENA(TCENA),
+         .TAA(TAA),
+         .TENB(TENB),
+         .TCENB(TCENB),
+         .TWENB(TWENB),
+         .TAB(TAB),
+         .TDB(TDB),
+         .RET1N(RET1N),
+         .SIA(SIA),
+         .SEA(SEA),
+         .DFTRAMBYP(DFTRAMBYP),
+         .SIB(SIB),
+         .SEB(SEB),
+         .COLLDISN(COLLDISN)
+   );
+
+endmodule // rf2_128x128_wm1_fr_top
+

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:45:59 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     avm
+#   AMCI Version:                  1.4.3-EAC
+#   avm_memcomp Version:       2.1.1-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_128x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 18022
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.81 0.81
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 8.73321e-05nF
+    VDDPE VSSE 5.62911e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 1.03174mA
+    VDDPE VSSE 3.05451mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 9.60653e-05nF
+    VDDPE VSSE 1.11025e-02nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 1.13492mA
+    VDDPE VSSE 35.83421mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 2.73427e-04nF
+    VDDPE VSSE 9.30121e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 2.40131mA
+    VDDPE VSSE 37.53301mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 9.86438e-05nF
+    VDDPE VSSE 4.13502e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 0.82264mA
+    VDDPE VSSE 23.27139mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 1.74783e-04nF
+    VDDPE VSSE 5.16619e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 1.64015mA
+    VDDPE VSSE 28.88487mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 8.14454e-06nF
+    VDDPE VSSE 9.88468e-03nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.14129mA
+    VDDPE VSSE 13.03296mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 8.14454e-06nF
+    VDDPE VSSE 9.88468e-03nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.14129mA
+    VDDPE VSSE 13.03296mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.69190e-05nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.87989e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 7.44800e-04mA
+    VDDPE VSSE 6.15800e-04mA
+  }
+  tsu 0.30495ns
+  ck2q_delay 1.15737ns
+  tr_q 0.034819ns
+  tf_q 0.039764ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.dat

@@ -0,0 +1,334 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:46:22 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     datatable
+#   AMCI Version:                  1.4.3-EAC
+#   datatable_memcomp Version:       1.3.0-amci
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	ss_0p81v_0p81v_m40c
+S	N
+geomx     	34.1250   
+geomy     	414.8600  
+volt      	0.8100    
+temp      	-40.0000  
+# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.2145	
+ttcenacenya	0.2108	
+ttenacenyapu	0.3026	
+ttenacenyanu	0.3541	
+tdftrambypcenya	0.3853	
+taaaya	0.2110	
+ttaaaya	0.2184	
+ttenaayapu	0.3904	
+ttenaayanu	0.3751	
+tdftrambypaya	0.3736	
+tcenbcenyb	0.2113	
+ttcenbcenyb	0.2108	
+ttenbcenybpu	0.3045	
+ttenbcenybnu	0.5445	
+tdftrambypcenyb	0.3738	
+twenbwenyb	0.2952	
+ttwenbwenyb	0.2956	
+ttenbwenybpu	0.6920	
+ttenbwenybnu	0.7096	
+tdftrambypwenyb	0.4014	
+tabayb	0.2105	
+ttabayb	0.2161	
+ttenbaybpu	0.5881	
+ttenbaybnu	0.5463	
+tdftrambypayb	0.3669	
+taccqa_rd0	1.0918	
+taccqa_rd1	1.1323	
+taccqa_rd2	1.1395	
+taccqa_rd3	1.1574	
+taccqa_rd4	1.2715	
+taccqa_rd5	1.3886	
+taccqa_rd6	1.5144	
+taccqa_rd7	1.6367	
+taccqa_scan0	1.0918	
+taccqa_scan1	1.1323	
+taccqa_scan2	1.1395	
+taccqa_scan3	1.1574	
+taccqa_scan4	1.2715	
+taccqa_scan5	1.3886	
+taccqa_scan6	1.5144	
+taccqa_scan7	1.6367	
+tclkasoa_rd0	1.1973	
+tclkasoa_rd1	1.2379	
+tclkasoa_rd2	1.2450	
+tclkasoa_rd3	1.2630	
+tclkasoa_rd4	1.3770	
+tclkasoa_rd5	1.4941	
+tclkasoa_rd6	1.6199	
+tclkasoa_rd7	1.7422	
+tclkasoa_scan0	1.1973	
+tclkasoa_scan1	1.2379	
+tclkasoa_scan2	1.2450	
+tclkasoa_scan3	1.2630	
+tclkasoa_scan4	1.3770	
+tclkasoa_scan5	1.4941	
+tclkasoa_scan6	1.6199	
+tclkasoa_scan7	1.7422	
+tclkbsob	0.5273	
+# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	3.3060	
+kload_aya	2.7500	
+kload_cenyb	3.3440	
+kload_wenyb	3.0700	
+kload_ayb	2.7720	
+kload_qa	1.0935	
+kload_soa	2.7600	
+kload_sob	3.1660	
+# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	1.6357	
+tcyca_ema1	1.6768	
+tcyca_ema2	1.6841	
+tcyca_ema3	1.7023	
+tcyca_ema4	1.8181	
+tcyca_ema5	1.9370	
+tcyca_ema6	2.0647	
+tcyca_ema7	2.1887	
+tcycb_ema0	1.8156	
+tcycb_ema1	1.9565	
+tcycb_ema2	2.0117	
+tcycb_ema3	2.1102	
+tcycb_ema4	2.2402	
+tcycb_ema5	2.3606	
+tcycb_ema6	2.5131	
+tcycb_ema7	2.6295	
+# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.8953	
+tcracwb_rd1	0.9358	
+tcracwb_rd2	0.9430	
+tcracwb_rd3	0.9609	
+tcracwb_rd4	1.0750	
+tcracwb_rd5	1.1921	
+tcracwb_rd6	1.3178	
+tcracwb_rd7	1.4401	
+tcwbcra_wr0	1.2617	
+tcwbcra_wr1	1.4005	
+tcwbcra_wr2	1.4549	
+tcwbcra_wr3	1.5519	
+tcwbcra_wr4	1.6800	
+tcwbcra_wr5	1.7986	
+tcwbcra_wr6	1.9488	
+tcwbcra_wr7	2.0636	
+# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.1789	
+tckal	0.1936	
+tckbh	0.1810	
+tckbl	0.1760	
+# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.2347	
+taas	0.3049	
+tcenbs	0.2335	
+twenbs	0.0857	
+tabs	0.3105	
+tdbs	0.1681	
+temaas	1.7857	
+temasas	1.7857	
+temabs	2.1935	
+ttenas	0.4955	
+ttcenas	0.2359	
+ttaas	0.3136	
+ttenbs	0.8276	
+ttcenbs	0.2341	
+ttwenbs	0.0862	
+ttabs	0.3176	
+ttdbs	0.1738	
+tsias	0.5450	
+tseas	0.5450	
+tdftrambypas	0.6851	
+tdftrambypbs	0.6851	
+tsibs	0.1681	
+tsebs	0.8276	
+tcolldisnas	1.7857	
+tcolldisnbs	2.1935	
+# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0852	
+tcenaf_ret1nfh	2.1743	
+tcenaf_ret1nrh	0.8350	
+taah	0.1420	
+tcenbh	0.0853	
+tcenbf_ret1nfh	2.1743	
+tcenbf_ret1nrh	0.8350	
+twenbh	0.3114	
+tabh	0.1304	
+tdbh	0.3013	
+temaah	2.4447	
+temasah	2.4447	
+temabh	2.6937	
+ttenah	0.1562	
+ttcenah	0.0869	
+ttcenaf_ret1nfh	2.1743	
+ttcenaf_ret1nrh	0.8350	
+ttaah	0.1420	
+ttenbh	0.3425	
+ttcenbh	0.0866	
+ttcenbf_ret1nfh	2.1743	
+ttcenbf_ret1nrh	0.8350	
+ttwenbh	0.3114	
+ttabh	0.1304	
+ttdbh	0.3013	
+tret1nf_dftrambypfh	0.0590	
+tret1nr_dftrambypfh	2.1743	
+tret1nf_cenbrh	0.0585	
+tret1nf_cenarh	0.0590	
+tret1nf_tcenarh	0.0590	
+tret1nf_tcenbrh	0.0585	
+tret1nr_tcenbrh	2.1743	
+tret1nr_tcenarh	1.7665	
+tret1nr_cenbrh	2.1743	
+tret1nr_cenarh	1.7665	
+tsiah	0.1246	
+tseah	2.4447	
+tdftrambypah	2.4447	
+tdftrambypbh	2.1743	
+tdftrambypr_ret1nfh	2.1743	
+tdftrambypr_ret1nrh	0.8350	
+tsibh	0.3013	
+tsebh	0.3425	
+tcolldisnah	2.4447	
+tcolldisnbh	2.6937	
+# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0087	
+icap_cena	0.0014	
+icap_aa	0.0017	
+icap_clkb	0.0088	
+icap_cenb	0.0011	
+icap_wenb	0.0016	
+icap_ab	0.0015	
+icap_db	0.0018	
+icap_emaa	0.0056	
+icap_emasa	0.0021	
+icap_emab	0.0054	
+icap_tena	0.0008	
+icap_tcena	0.0012	
+icap_taa	0.0016	
+icap_tenb	0.0009	
+icap_tcenb	0.0012	
+icap_twenb	0.0014	
+icap_tab	0.0014	
+icap_tdb	0.0015	
+icap_sia	0.0011	
+icap_sea	0.0016	
+icap_dftrambyp	0.0016	
+icap_sib	0.0054	
+icap_seb	0.0017	
+icap_colldisn	0.0021	
+icap_ret1n	0.0032	
+# High Density Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	7.448e-04	
+icc_standby_p_chipdisable	6.158e-04	
+icc_standby_c_ret1	7.390e-04	
+icc_standby_p_ret1	4.217e-06	
+icc_standby_c_selective_precharge	7.374e-04	
+icc_standby_p_selective_precharge	2.993e-04	
+icc_c_rd0_a	7.956e-05	
+icc_c_rd1_a	7.990e-05	
+icc_c_rd2_a	7.990e-05	
+icc_c_rd3_a	7.990e-05	
+icc_c_rd4_a	8.153e-05	
+icc_c_rd5_a	8.273e-05	
+icc_c_rd6_a	8.288e-05	
+icc_c_rd7_a	8.288e-05	
+icc_p_rd0_a	3.278e-03	
+icc_p_rd1_a	3.333e-03	
+icc_p_rd2_a	3.333e-03	
+icc_p_rd3_a	3.349e-03	
+icc_p_rd4_a	3.423e-03	
+icc_p_rd5_a	3.447e-03	
+icc_p_rd6_a	3.475e-03	
+icc_p_rd7_a	3.475e-03	
+icc_c_wr0_b	1.412e-04	
+icc_c_wr1_b	1.416e-04	
+icc_c_wr2_b	1.416e-04	
+icc_c_wr3_b	1.416e-04	
+icc_c_wr4_b	1.432e-04	
+icc_c_wr5_b	1.444e-04	
+icc_c_wr6_b	1.446e-04	
+icc_c_wr7_b	1.446e-04	
+icc_p_wr0_b	4.113e-03	
+icc_p_wr1_b	4.168e-03	
+icc_p_wr2_b	4.168e-03	
+icc_p_wr3_b	4.185e-03	
+icc_p_wr4_b	4.258e-03	
+icc_p_wr5_b	4.282e-03	
+icc_p_wr6_b	4.310e-03	
+icc_p_wr7_b	4.310e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	5.764e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	8.893e-04	
+icc_c_peak	2.401311	
+icc_p_peak	37.533005	
+icc_c_inrush	1.111213	
+icc_p_inrush	35.745719	

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_tt_0p90v_0p90v_25c.avm

@@ -0,0 +1,162 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:46:06 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     avm
+#   AMCI Version:                  1.4.3-EAC
+#   avm_memcomp Version:       2.1.1-EAC
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+rf2_128x128_wm1 {
+  MEMORY_TYPE RegFile
+  EQUIV_GATE_COUNT 18022
+  VDD_PIN VDDCE VDDPE
+  GND_PIN VSSE
+  #This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
+  #However, RedHawk needs the process to be specified as 'PROCESS XX'
+  PROCESS XX
+  Cload 3.5e-05nF
+  VDD 0.9 0.9
+
+  state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
+  state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
+  state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
+  state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
+  state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
+  state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
+  state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
+ 
+  Cpd avm_into_lowpwr {
+    VDDCE VSSE 9.28407e-05nF
+    VDDPE VSSE 5.69523e-04nF
+  }
+  PEAK_I avm_into_lowpwr {
+    VDDCE VSSE 1.89595mA
+    VDDPE VSSE 5.29014mA
+  }
+  Cpd avm_outof_lowpwr {
+    VDDCE VSSE 1.02125e-04nF
+    VDDPE VSSE 1.14681e-02nF
+  }
+  PEAK_I avm_outof_lowpwr {
+    VDDCE VSSE 2.08555mA
+    VDDPE VSSE 63.53755mA
+  }
+  Cpd avm_read_write {
+    VDDCE VSSE 3.13542e-04nF
+    VDDPE VSSE 9.52395e-03nF
+  }
+  PEAK_I avm_read_write {
+    VDDCE VSSE 4.53049mA
+    VDDPE VSSE 66.71443mA
+  }
+  Cpd avm_read_desel {
+    VDDCE VSSE 1.00162e-04nF
+    VDDPE VSSE 4.27128e-03nF
+  }
+  PEAK_I avm_read_desel {
+    VDDCE VSSE 1.38012mA
+    VDDPE VSSE 39.33253mA
+  }
+  Cpd avm_desel_write {
+    VDDCE VSSE 2.13380e-04nF
+    VDDPE VSSE 5.25267e-03nF
+  }
+  PEAK_I avm_desel_write {
+    VDDCE VSSE 3.15716mA
+    VDDPE VSSE 55.27448mA
+  }
+  Cpd avm_scan_capture {
+    VDDCE VSSE 8.56193e-06nF
+    VDDPE VSSE 1.02363e-02nF
+  }
+  PEAK_I avm_scan_capture {
+    VDDCE VSSE 0.27530mA
+    VDDPE VSSE 24.42748mA
+  }
+  Cpd avm_scan_shift {
+    VDDCE VSSE 8.56193e-06nF
+    VDDPE VSSE 1.02363e-02nF
+  }
+  PEAK_I avm_scan_shift {
+    VDDCE VSSE 0.27530mA
+    VDDPE VSSE 24.42748mA
+  }
+  Cpd standby_trig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.77000e-05nF
+  }
+  Cpd standby_ntrig {
+    VDDCE VSSE 0.00000e+00nF
+    VDDPE VSSE 1.96666e-05nF
+  }
+  LEAKAGE_I {
+    VDDCE VSSE 6.50200e-03mA
+    VDDPE VSSE 1.13860e-02mA
+  }
+  tsu 0.145088ns
+  ck2q_delay 0.68828ns
+  tr_q 0.01885ns
+  tf_q 0.022375ns
+  CHARACTERIZATION_MODE accurate
+}

hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_tt_0p90v_0p90v_25c.dat

@@ -0,0 +1,334 @@
+#
+# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+#
+# Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+#
+# Use of this Software is subject to the terms and conditions of the
+# applicable license agreement with ARM Physical IP, Inc.
+# In addition, this Software is protected by patents, copyright law 
+# and international treaties.
+#
+# The copyright notice(s) in this Software does not indicate actual or
+# intended publication of this Software.
+#
+# Compiler Name: High Density Two Port Register File SVT MVT Compiler
+#
+# Creation Date: Sun Oct 20 14:46:27 2019
+#
+# Instance Options:
+#   Instance Name:                 rf2_128x128_wm1
+#   Number of Words:               128
+#   Number of Bits:                128
+#   Multiplexer Width:             2
+#   Multi-Vt selection:            BASE
+#   Frequency <MHz>:               1
+#   Activity Factor <%>:           50
+#   Pipeline:                      off
+#   Word-Write Mask:               on
+#   Word Partition Size:           1
+#   Write through:                 off
+#   Top Metal Layer:               m5-m10
+#   Power Type:                    otc
+#   Redundancy:                    off
+#   Redundant Columns:             2
+#   Redundant Rows:                0
+#   BIST MUXes:                    on
+#   Soft Error Repair (SER):       none
+#   Power Gating:                  off
+#   Back Biasing:                  off
+#   Retention:                     on
+#   Extra Margin Adjustment:       on
+#   Advanced Test Features:        off
+#   Customer Comment:              This is a memory instance
+#   Bus-notation:                  on
+#   Power Ground Rename:           vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+#   Name Case:                     upper
+#   Check Instance Name:           off
+#   Diodes:                        on
+#   Drive Strength:                6
+#   Site Definitions:              off
+#   Library Name:                  USERLIB
+#   Liberty setting:               nldm
+#
+# Compiler Versions:
+#   Memory Version:                r4p0
+#   Lang compiler Version:         4.1.6-EAC2
+#   View Name:                     datatable
+#   AMCI Version:                  1.4.3-EAC
+#   datatable_memcomp Version:       1.3.0-amci
+#
+# Modeling Assumptions: N/A
+#
+# Modeling Limitations: N/A
+#
+# Known Bugs: N/A
+#
+# Known Work Arounds: N/A
+#
+# Units used in Datatable :
+#   geomx:                         micron
+#   geomy:                         micron
+#   Voltage:                       volts
+#   Temprature:                    Degree Celsius
+#   Current:                       mA
+#   Time:                          ns
+#
+name      	tt_0p90v_0p90v_25c
+S	N
+geomx     	34.1250   
+geomy     	414.8600  
+volt      	0.9000    
+temp      	25.0000   
+# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
+tcenacenya	0.1187	
+ttcenacenya	0.1176	
+ttenacenyapu	0.1613	
+ttenacenyanu	0.1885	
+tdftrambypcenya	0.1900	
+taaaya	0.1038	
+ttaaaya	0.1082	
+ttenaayapu	0.1877	
+ttenaayanu	0.1835	
+tdftrambypaya	0.1776	
+tcenbcenyb	0.1195	
+ttcenbcenyb	0.1185	
+ttenbcenybpu	0.1658	
+ttenbcenybnu	0.2823	
+tdftrambypcenyb	0.1824	
+twenbwenyb	0.1351	
+ttwenbwenyb	0.1341	
+ttenbwenybpu	0.3463	
+ttenbwenybnu	0.3615	
+tdftrambypwenyb	0.2183	
+tabayb	0.1040	
+ttabayb	0.1062	
+ttenbaybpu	0.2796	
+ttenbaybnu	0.2792	
+tdftrambypayb	0.1779	
+taccqa_rd0	0.6543	
+taccqa_rd1	0.6758	
+taccqa_rd2	0.6787	
+taccqa_rd3	0.6883	
+taccqa_rd4	0.7447	
+taccqa_rd5	0.7988	
+taccqa_rd6	0.8541	
+taccqa_rd7	0.9079	
+taccqa_scan0	0.6543	
+taccqa_scan1	0.6758	
+taccqa_scan2	0.6787	
+taccqa_scan3	0.6883	
+taccqa_scan4	0.7447	
+taccqa_scan5	0.7988	
+taccqa_scan6	0.8541	
+taccqa_scan7	0.9079	
+tclkasoa_rd0	0.6847	
+tclkasoa_rd1	0.7062	
+tclkasoa_rd2	0.7091	
+tclkasoa_rd3	0.7187	
+tclkasoa_rd4	0.7751	
+tclkasoa_rd5	0.8292	
+tclkasoa_rd6	0.8845	
+tclkasoa_rd7	0.9383	
+tclkasoa_scan0	0.6847	
+tclkasoa_scan1	0.7062	
+tclkasoa_scan2	0.7091	
+tclkasoa_scan3	0.7187	
+tclkasoa_scan4	0.7751	
+tclkasoa_scan5	0.8292	
+tclkasoa_scan6	0.8845	
+tclkasoa_scan7	0.9383	
+tclkbsob	0.2967	
+# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
+kload_cenya	2.0800	
+kload_aya	1.6620	
+kload_cenyb	1.9640	
+kload_wenyb	1.7940	
+kload_ayb	1.6740	
+kload_qa	0.6365	
+kload_soa	1.7020	
+kload_sob	1.8420	
+# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
+tcyca_ema0	0.9522	
+tcyca_ema1	0.9740	
+tcyca_ema2	0.9769	
+tcyca_ema3	0.9867	
+tcyca_ema4	1.0440	
+tcyca_ema5	1.0989	
+tcyca_ema6	1.1550	
+tcyca_ema7	1.2096	
+tcycb_ema0	1.0059	
+tcycb_ema1	1.0742	
+tcycb_ema2	1.0979	
+tcycb_ema3	1.1427	
+tcycb_ema4	1.2141	
+tcycb_ema5	1.2663	
+tcycb_ema6	1.3352	
+tcycb_ema7	1.3854	
+# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
+tcracwb_rd0	0.6349	
+tcracwb_rd1	0.6563	
+tcracwb_rd2	0.6593	
+tcracwb_rd3	0.6689	
+tcracwb_rd4	0.7252	
+tcracwb_rd5	0.7794	
+tcracwb_rd6	0.8347	
+tcracwb_rd7	0.8885	
+tcwbcra_wr0	0.7842	
+tcwbcra_wr1	0.8515	
+tcwbcra_wr2	0.8748	
+tcwbcra_wr3	0.9189	
+tcwbcra_wr4	0.9892	
+tcwbcra_wr5	1.0406	
+tcwbcra_wr6	1.1085	
+tcwbcra_wr7	1.1581	
+# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
+tckah	0.1135	
+tckal	0.1131	
+tckbh	0.1160	
+tckbl	0.1128	
+# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
+tcenas	0.1224	
+taas	0.1451	
+tcenbs	0.1250	
+twenbs	0.0225	
+tabs	0.1537	
+tdbs	0.0487	
+temaas	1.0264	
+temasas	1.0264	
+temabs	1.1825	
+ttenas	0.2524	
+ttcenas	0.1224	
+ttaas	0.1495	
+ttenbs	0.4747	
+ttcenbs	0.1262	
+ttwenbs	0.0225	
+ttabs	0.1572	
+ttdbs	0.0509	
+tsias	0.2777	
+tseas	0.2777	
+tdftrambypas	0.3304	
+tdftrambypbs	0.3304	
+tsibs	0.0487	
+tsebs	0.4747	
+tcolldisnas	1.0264	
+tcolldisnbs	1.1825	
+# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
+tcenah	0.0495	
+tcenaf_ret1nfh	1.1859	
+tcenaf_ret1nrh	0.4629	
+taah	0.0840	
+tcenbh	0.0496	
+tcenbf_ret1nfh	1.1859	
+tcenbf_ret1nrh	0.4629	
+twenbh	0.2057	
+tabh	0.0791	
+tdbh	0.1941	
+temaah	1.3375	
+temasah	1.3375	
+temabh	1.4286	
+ttenah	0.0924	
+ttcenah	0.0524	
+ttcenaf_ret1nfh	1.1859	
+ttcenaf_ret1nrh	0.4629	
+ttaah	0.0840	
+ttenbh	0.2271	
+ttcenbh	0.0510	
+ttcenbf_ret1nfh	1.1859	
+ttcenbf_ret1nrh	0.4629	
+ttwenbh	0.2065	
+ttabh	0.0791	
+ttdbh	0.1941	
+tret1nf_dftrambypfh	0.0315	
+tret1nr_dftrambypfh	1.1859	
+tret1nf_cenbrh	0.0315	
+tret1nf_cenarh	0.0306	
+tret1nf_tcenarh	0.0306	
+tret1nf_tcenbrh	0.0315	
+tret1nr_tcenbrh	1.1859	
+tret1nr_tcenarh	1.0299	
+tret1nr_cenbrh	1.1859	
+tret1nr_cenarh	1.0299	
+tsiah	0.0817	
+tseah	1.3375	
+tdftrambypah	1.3375	
+tdftrambypbh	1.1859	
+tdftrambypr_ret1nfh	1.1859	
+tdftrambypr_ret1nrh	0.4629	
+tsibh	0.1941	
+tsebh	0.2271	
+tcolldisnah	1.3375	
+tcolldisnbh	1.4286	
+# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
+icap_clka	0.0091	
+icap_cena	0.0013	
+icap_aa	0.0016	
+icap_clkb	0.0097	
+icap_cenb	0.0013	
+icap_wenb	0.0014	
+icap_ab	0.0016	
+icap_db	0.0019	
+icap_emaa	0.0058	
+icap_emasa	0.0025	
+icap_emab	0.0056	
+icap_tena	0.0009	
+icap_tcena	0.0014	
+icap_taa	0.0015	
+icap_tenb	0.0010	
+icap_tcenb	0.0014	
+icap_twenb	0.0012	
+icap_tab	0.0016	
+icap_tdb	0.0016	
+icap_sia	0.0012	
+icap_sea	0.0016	
+icap_dftrambyp	0.0021	
+icap_sib	0.0058	
+icap_seb	0.0019	
+icap_colldisn	0.0021	
+icap_ret1n	0.0034	
+# High Density Two Port Register File SVT MVT Compiler : current specific information.
+icc_standby_c_chipdisable	6.502e-03	
+icc_standby_p_chipdisable	0.011386	
+icc_standby_c_ret1	6.767e-03	
+icc_standby_p_ret1	7.153e-04	
+icc_standby_c_selective_precharge	6.351e-03	
+icc_standby_p_selective_precharge	9.266e-03	
+icc_c_rd0_a	8.934e-05	
+icc_c_rd1_a	9.015e-05	
+icc_c_rd2_a	9.015e-05	
+icc_c_rd3_a	9.015e-05	
+icc_c_rd4_a	9.237e-05	
+icc_c_rd5_a	9.357e-05	
+icc_c_rd6_a	9.515e-05	
+icc_c_rd7_a	9.515e-05	
+icc_p_rd0_a	3.756e-03	
+icc_p_rd1_a	3.815e-03	
+icc_p_rd2_a	3.821e-03	
+icc_p_rd3_a	3.844e-03	
+icc_p_rd4_a	3.951e-03	
+icc_p_rd5_a	4.016e-03	
+icc_p_rd6_a	4.024e-03	
+icc_p_rd7_a	4.035e-03	
+icc_c_wr0_b	1.912e-04	
+icc_c_wr1_b	1.920e-04	
+icc_c_wr2_b	1.920e-04	
+icc_c_wr3_b	1.920e-04	
+icc_c_wr4_b	1.943e-04	
+icc_c_wr5_b	1.955e-04	
+icc_c_wr6_b	1.971e-04	
+icc_c_wr7_b	1.971e-04	
+icc_p_wr0_b	4.639e-03	
+icc_p_wr1_b	4.698e-03	
+icc_p_wr2_b	4.704e-03	
+icc_p_wr3_b	4.727e-03	
+icc_p_wr4_b	4.834e-03	
+icc_p_wr5_b	4.899e-03	
+icc_p_wr6_b	4.907e-03	
+icc_p_wr7_b	4.918e-03	
+icc_c_desela	0.000e+00	
+icc_p_desela	6.716e-05	
+icc_c_deselb	0.000e+00	
+icc_p_deselb	1.019e-03	
+icc_c_peak	4.530492	
+icc_p_peak	66.714427	
+icc_c_inrush	2.342644	
+icc_p_inrush	63.53755	

hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.memlib

@@ -0,0 +1,360 @@
+/* logicvision_memcomp Version: c0.1.2-beta */
+/* common_memcomp Version: c0.1.0-EAC */
+/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
+//
+//       CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
+//      
+//       Copyright (c) 1993 - 2019 ARM Physical IP, Inc.  All Rights Reserved.
+//      
+//       Use of this Software is subject to the terms and conditions of the
+//       applicable license agreement with ARM Physical IP, Inc.
+//       In addition, this Software is protected by patents, copyright law 
+//       and international treaties.
+//      
+//       The copyright notice(s) in this Software does not indicate actual or
+//       intended publication of this Software.
+//
+//      logicvision model for High Density Two Port Register File SVT MVT Compiler
+//
+//      Instance Name:              rf2_256x128_wm1
+//      Words:                      256
+//      Bits:                       128
+//      Mux:                        2
+//      Drive:                      6
+//      Write Mask:                 On
+//      Extra Margin Adjustment:    On
+//      Redundant Rows:             0
+//      Redundant Columns:          2
+//      Test Muxes                  On
+//
+//      Creation Date:  Sun Oct 20 14:37:44 2019
+//      Version: 	r4p0
+//
+//      Modeling Assumptions: 
+//
+//      Modeling Limitations: None
+//
+//      Known Bugs: None.
+//
+//      Known Work Arounds: N/A
+//
+MemoryTemplate (rf2_256x128_wm1) {
+	Algorithm : SmarchChkbvcd;
+	DataOutStage : None;
+	LogicalPorts : 1R1W;
+	BitGrouping : 1;
+	MemoryType : SRAM;
+	MinHold : 0.5;
+	OperationSet : SyncWRvcd;
+	SelectDuringWriteThru : Off;
+	ShadowRead : On;
+	ShadowWrite : On;
+        TransparentMode : None;
+        ObservationLogic: On;
+        InternalScanLogic: On;
+	CellName : rf2_256x128_wm1;
+	NumberOfWords : 256;
+	AddressCounter{
+		Function (Address) {
+			LogicalAddressMap{
+				ColumnAddress[0] : Address[0];
+				RowAddress[6:0] : Address[7:1];
+			}
+		}
+		Function (ColumnAddress) {
+			CountRange [0:1];
+			}
+		Function (RowAddress) {
+			CountRange [0:127];
+		}
+	}
+	PhysicalAddressMap{
+		ColumnAddress[0] : c[0];
+		RowAddress[0] : r[0];
+		RowAddress[1] : r[1];
+		RowAddress[2] : r[2];
+		RowAddress[3] : r[3];
+		RowAddress[4] : r[4];
+		RowAddress[5] : r[5];
+		RowAddress[6] : r[6];
+	}
+	PhysicalDataMap{
+		Data[0] : NOT d[0];
+		Data[1] : NOT d[1];
+		Data[2] : NOT d[2];
+		Data[3] : NOT d[3];
+		Data[4] : NOT d[4];
+		Data[5] : NOT d[5];
+		Data[6] : NOT d[6];
+		Data[7] : NOT d[7];
+		Data[8] : NOT d[8];
+		Data[9] : NOT d[9];
+		Data[10] : NOT d[10];
+		Data[11] : NOT d[11];
+		Data[12] : NOT d[12];
+		Data[13] : NOT d[13];
+		Data[14] : NOT d[14];
+		Data[15] : NOT d[15];
+		Data[16] : NOT d[16];
+		Data[17] : NOT d[17];
+		Data[18] : NOT d[18];
+		Data[19] : NOT d[19];
+		Data[20] : NOT d[20];
+		Data[21] : NOT d[21];
+		Data[22] : NOT d[22];
+		Data[23] : NOT d[23];
+		Data[24] : NOT d[24];
+		Data[25] : NOT d[25];
+		Data[26] : NOT d[26];
+		Data[27] : NOT d[27];
+		Data[28] : NOT d[28];
+		Data[29] : NOT d[29];
+		Data[30] : NOT d[30];
+		Data[31] : NOT d[31];
+		Data[32] : NOT d[32];
+		Data[33] : NOT d[33];
+		Data[34] : NOT d[34];
+		Data[35] : NOT d[35];
+		Data[36] : NOT d[36];
+		Data[37] : NOT d[37];
+		Data[38] : NOT d[38];
+		Data[39] : NOT d[39];
+		Data[40] : NOT d[40];
+		Data[41] : NOT d[41];
+		Data[42] : NOT d[42];
+		Data[43] : NOT d[43];
+		Data[44] : NOT d[44];
+		Data[45] : NOT d[45];
+		Data[46] : NOT d[46];
+		Data[47] : NOT d[47];
+		Data[48] : NOT d[48];
+		Data[49] : NOT d[49];
+		Data[50] : NOT d[50];
+		Data[51] : NOT d[51];
+		Data[52] : NOT d[52];
+		Data[53] : NOT d[53];
+		Data[54] : NOT d[54];
+		Data[55] : NOT d[55];
+		Data[56] : NOT d[56];
+		Data[57] : NOT d[57];
+		Data[58] : NOT d[58];
+		Data[59] : NOT d[59];
+		Data[60] : NOT d[60];
+		Data[61] : NOT d[61];
+		Data[62] : NOT d[62];
+		Data[63] : NOT d[63];
+		Data[64] : d[64];
+		Data[65] : d[65];
+		Data[66] : d[66];
+		Data[67] : d[67];
+		Data[68] : d[68];
+		Data[69] : d[69];
+		Data[70] : d[70];
+		Data[71] : d[71];
+		Data[72] : d[72];
+		Data[73] : d[73];
+		Data[74] : d[74];
+		Data[75] : d[75];
+		Data[76] : d[76];
+		Data[77] : d[77];
+		Data[78] : d[78];
+		Data[79] : d[79];
+		Data[80] : d[80];
+		Data[81] : d[81];
+		Data[82] : d[82];
+		Data[83] : d[83];
+		Data[84] : d[84];
+		Data[85] : d[85];
+		Data[86] : d[86];
+		Data[87] : d[87];
+		Data[88] : d[88];
+		Data[89] : d[89];
+		Data[90] : d[90];
+		Data[91] : d[91];
+		Data[92] : d[92];
+		Data[93] : d[93];
+		Data[94] : d[94];
+		Data[95] : d[95];
+		Data[96] : d[96];
+		Data[97] : d[97];
+		Data[98] : d[98];
+		Data[99] : d[99];
+		Data[100] : d[100];
+		Data[101] : d[101];
+		Data[102] : d[102];
+		Data[103] : d[103];
+		Data[104] : d[104];
+		Data[105] : d[105];
+		Data[106] : d[106];
+		Data[107] : d[107];
+		Data[108] : d[108];
+		Data[109] : d[109];
+		Data[110] : d[110];
+		Data[111] : d[111];
+		Data[112] : d[112];
+		Data[113] : d[113];
+		Data[114] : d[114];
+		Data[115] : d[115];
+		Data[116] : d[116];
+		Data[117] : d[117];
+		Data[118] : d[118];
+		Data[119] : d[119];
+		Data[120] : d[120];
+		Data[121] : d[121];
+		Data[122] : d[122];
+		Data[123] : d[123];
+		Data[124] : d[124];
+		Data[125] : d[125];
+		Data[126] : d[126];
+		Data[127] : d[127];
+	}
+	Port (AA[7:0]) {
+		Function : Address;
+		LogicalPort : A;
+		EmbeddedTestLogic {
+			TestInput : TAA[7:0];
+			TestOutput : AYA[7:0];
+		}
+	}
+	Port (QA[127:0]) {
+		Function : Data;
+		Direction : output;
+		LogicalPort : A;
+	}
+	Port (CENA) {
+		Function : ReadEnable;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENA;
+			TestOutput : CENYA;
+		}
+	}
+	Port (TENA) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveLow;
+	}
+	Port (CLKA) {
+		Function : Clock;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAA[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+	Port (EMASA) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : A;
+		Polarity : ActiveHigh;
+	}
+  port (SEA){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIA[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOA[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+  port (DFTRAMBYP){
+          Function : ScanTest;
+          Direction : Input;
+          Polarity : ActiveHigh;
+  }
+	Port (AB[7:0]) {
+		Function : Address;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TAB[7:0];
+			TestOutput : AYB[7:0];
+		}
+	}
+	Port (DB[127:0]) {
+		Function : Data;
+		Direction : input;
+		LogicalPort : B;
+		EmbeddedTestLogic {
+			TestInput : TDB[127:0];
+		}
+	}
+	Port (WENB[127:0]) {
+		Function : GroupWriteEnable;
+                BitsPerWriteEnable: 1;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TWENB[127:0];
+			TestOutput : WENYB[127:0];
+		}
+	}
+	Port (CENB) {
+		Function : WriteEnable;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+		EmbeddedTestLogic {
+			TestInput : TCENB;
+			TestOutput : CENYB;
+		}
+	}
+	Port (TENB) {
+		Function : BISTOn;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveLow;
+	}
+	Port (CLKB) {
+		Function : Clock;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (EMAB[2:0]) {
+		Function : None;
+		SafeValue : 0;
+		Direction : Input;
+		LogicalPort : B;
+		Polarity : ActiveHigh;
+	}
+	Port (COLLDISN) {
+             Function : None;
+             SafeValue : 1;
+             Direction : Input;
+             Polarity : ActiveLow;
+       }
+  port (SEB){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SIB[1:0]){
+          Function : None;
+          Direction : Input;
+          SafeValue : 0;
+          Polarity : ActiveHigh;
+  }
+  port (SOB[1:0]){
+          Function : None;
+          Direction : Output;
+  }
+	port (RET1N){
+		Function : None;
+		Direction : Input;
+		SafeValue : 1;
+		Polarity : Activelow;
+	}
+}