pipeline refactoring
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@@ -8,7 +8,6 @@ module VX_gpr_mux (
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// outputs
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VX_alu_req_if alu_req_if,
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VX_branch_req_if branch_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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@@ -16,7 +15,6 @@ module VX_gpr_mux (
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);
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wire[`NUM_THREADS-1:0] is_alu = {`NUM_THREADS{execute_if.ex_type == `EX_ALU}};
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wire[`NUM_THREADS-1:0] is_br = {`NUM_THREADS{execute_if.ex_type == `EX_BR}};
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wire[`NUM_THREADS-1:0] is_lsu = {`NUM_THREADS{execute_if.ex_type == `EX_LSU}};
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wire[`NUM_THREADS-1:0] is_csr = {`NUM_THREADS{execute_if.ex_type == `EX_CSR}};
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wire[`NUM_THREADS-1:0] is_mul = {`NUM_THREADS{execute_if.ex_type == `EX_MUL}};
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@@ -31,18 +29,8 @@ module VX_gpr_mux (
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assign alu_req_if.wb = execute_if.wb;
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assign alu_req_if.rs1_data = rs1_data;
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assign alu_req_if.rs2_data = rs2_data;
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// BR unit
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assign branch_req_if.valid = execute_if.valid & is_br;
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assign branch_req_if.warp_num = execute_if.warp_num;
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assign branch_req_if.curr_PC = execute_if.curr_PC;
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assign branch_req_if.br_op = `BR_OP(execute_if.instr_op);
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assign branch_req_if.offset = execute_if.imm;
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assign branch_req_if.next_PC = execute_if.next_PC;
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assign branch_req_if.rs1_data = rs1_data;
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assign branch_req_if.rs2_data = rs2_data;
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assign branch_req_if.rd = execute_if.rd;
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assign branch_req_if.wb = execute_if.wb;
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assign alu_req_if.offset = execute_if.imm;
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assign alu_req_if.next_PC = execute_if.next_PC;
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// LSU unit
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assign lsu_req_if.valid = execute_if.valid & is_lsu;
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