From e0905f8352a696418ce557ac695121aa1f6fafd6 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 9 Dec 2020 05:34:27 -0800 Subject: [PATCH] minor update --- ci/blackbox.sh | 17 +++- hw/rtl/VX_dcache_arb.v | 73 +++++----------- hw/rtl/VX_instr_demux.v | 131 +++++++++++++++------------- hw/rtl/fp_cores/altera/acl_fdiv.sv | 2 +- hw/rtl/fp_cores/altera/acl_fsqrt.sv | 2 +- hw/rtl/fp_cores/altera/acl_ftoi.sv | 2 +- hw/rtl/fp_cores/altera/acl_ftou.sv | 2 +- hw/rtl/fp_cores/altera/acl_itof.sv | 2 +- hw/rtl/fp_cores/altera/acl_utof.sv | 2 +- hw/rtl/libs/VX_skid_buffer.v | 21 ++++- hw/syn/quartus/project.sdc | 2 +- 11 files changed, 133 insertions(+), 123 deletions(-) diff --git a/ci/blackbox.sh b/ci/blackbox.sh index 01373004..2dd2a905 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -62,7 +62,6 @@ case $i in ;; --scope) SCOPE=1 - SCOPE_FLAG=-DSCOPE shift ;; --perf) @@ -130,7 +129,7 @@ case $APP in ;; esac -CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS -DL2_ENABLE=$L2 -DL3_ENABLE=$L3 $PERF_FLAG $SCOPE_FLAG" +CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS -DL2_ENABLE=$L2 -DL3_ENABLE=$L3 $PERF_FLAG" echo "CONFIGS=$CONFIGS" @@ -138,7 +137,12 @@ make -C $DRIVER_PATH clean if [ $DEBUG -eq 1 ] then - DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + if [ $SCOPE -eq 1 ] + then + DEBUG=1 SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + else + DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + fi if [ $HAS_ARGS -eq 1 ] then @@ -147,7 +151,12 @@ then make -C $APP_PATH run-$DRIVER > run.log 2>&1 fi else - CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + if [ $SCOPE -eq 1 ] + then + SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + else + CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + fi if [ $HAS_ARGS -eq 1 ] then diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v index 45d1dfec..d6670ca9 100644 --- a/hw/rtl/VX_dcache_arb.v +++ b/hw/rtl/VX_dcache_arb.v @@ -23,69 +23,44 @@ module VX_dcache_arb ( localparam REQ_DATAW = `NUM_THREADS + 1 + `NUM_THREADS * `DWORD_SIZE + `NUM_THREADS * (32-`CLOG2(`DWORD_SIZE)) + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH; - // - // input request buffer - // - - VX_cache_core_req_if #( - .NUM_REQS(`DNUM_REQUESTS), - .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_req_qual_if(); - wire core_req_valid; - - VX_skid_buffer #( - .DATAW (REQ_DATAW) - ) req_buffer ( - .clk (clk), - .reset (reset), - .valid_in ((| core_req_if.valid)), - .data_in ({core_req_if.valid, core_req_if.rw, core_req_if.byteen, core_req_if.addr, core_req_if.data, core_req_if.tag}), - .ready_in (core_req_if.ready), - .valid_out (core_req_valid), - .data_out ({core_req_qual_if.valid, core_req_qual_if.rw, core_req_qual_if.byteen, core_req_qual_if.addr, core_req_qual_if.data, core_req_qual_if.tag}), - .ready_out (core_req_qual_if.ready) - ); - // // select request // // select shared memory bus - wire is_smem_addr = core_req_valid - && ({core_req_qual_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR) - && ({core_req_qual_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE)); + wire is_smem_addr = (| core_req_if.valid) + && ({core_req_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR) + && ({core_req_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE)); // select io bus - wire is_io_addr = core_req_valid - && ({core_req_qual_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); + wire is_io_addr = (| core_req_if.valid) + && ({core_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); reg [2:0] req_select; reg req_ready; - assign cache_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[0]}}; - assign cache_req_if.rw = core_req_qual_if.rw; - assign cache_req_if.byteen = core_req_qual_if.byteen; - assign cache_req_if.addr = core_req_qual_if.addr; - assign cache_req_if.data = core_req_qual_if.data; - assign cache_req_if.tag = core_req_qual_if.tag; + assign cache_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[0]}}; + assign cache_req_if.rw = core_req_if.rw; + assign cache_req_if.byteen = core_req_if.byteen; + assign cache_req_if.addr = core_req_if.addr; + assign cache_req_if.data = core_req_if.data; + assign cache_req_if.tag = core_req_if.tag; - assign smem_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[1]}}; - assign smem_req_if.rw = core_req_qual_if.rw; - assign smem_req_if.byteen = core_req_qual_if.byteen; - assign smem_req_if.addr = core_req_qual_if.addr; - assign smem_req_if.data = core_req_qual_if.data; - assign smem_req_if.tag = core_req_qual_if.tag; + assign smem_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[1]}}; + assign smem_req_if.rw = core_req_if.rw; + assign smem_req_if.byteen = core_req_if.byteen; + assign smem_req_if.addr = core_req_if.addr; + assign smem_req_if.data = core_req_if.data; + assign smem_req_if.tag = core_req_if.tag; - assign io_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[2]}}; - assign io_req_if.rw = core_req_qual_if.rw; - assign io_req_if.byteen = core_req_qual_if.byteen; - assign io_req_if.addr = core_req_qual_if.addr; - assign io_req_if.data = core_req_qual_if.data; - assign io_req_if.tag = core_req_qual_if.tag; + assign io_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[2]}}; + assign io_req_if.rw = core_req_if.rw; + assign io_req_if.byteen = core_req_if.byteen; + assign io_req_if.addr = core_req_if.addr; + assign io_req_if.data = core_req_if.data; + assign io_req_if.tag = core_req_if.tag; - assign core_req_qual_if.ready = req_ready; + assign core_req_if.ready = req_ready; always @(*) begin req_select = 0; diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index 67bc3eb3..99409a17 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -30,72 +30,77 @@ module VX_instr_demux ( // ALU unit wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU); - wire alu_stall = alu_req_if.valid && ~alu_req_if.ready; + wire alu_req_ready; wire is_br_op = `IS_BR_MOD(execute_if.op_mod); - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), - .R (1) - ) alu_pipe ( - .clk (clk), - .reset (reset), - .stall (alu_stall), - .flush (1'b0), - .data_in ({alu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}) + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), + .REGISTER (1) // ALU has no back pressure, use a simple register + ) alu_buffer ( + .clk (clk), + .reset (reset), + .valid_in (alu_req_valid), + .ready_in (alu_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), + .valid_out (alu_req_if.valid), + .ready_out (alu_req_if.ready) ); // lsu unit wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU); - wire lsu_stall = lsu_req_if.valid && ~lsu_req_if.ready; + wire lsu_req_ready; - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), - .R (1) - ) lsu_pipe ( + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)) + ) lsu_buffer ( .clk (clk), .reset (reset), - .stall (lsu_stall), - .flush (1'b0), - .data_in ({lsu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}) + .valid_in (lsu_req_valid), + .ready_in (lsu_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), + .valid_out (lsu_req_if.valid), + .ready_out (lsu_req_if.ready) ); // csr unit wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR); - wire csr_stall = csr_req_if.valid && ~csr_req_if.ready; + wire csr_req_ready; - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), - .R (1) - ) csr_pipe ( + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32) + ) csr_buffer ( .clk (clk), .reset (reset), - .stall (csr_stall), - .flush (1'b0), - .data_in ({csr_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}), - .data_out ({csr_req_if.valid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data}) + .valid_in (csr_req_valid), + .ready_in (csr_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}), + .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data}), + .valid_out (csr_req_if.valid), + .ready_out (csr_req_if.ready) ); // mul unit `ifdef EXT_M_ENABLE wire mul_req_valid = execute_if.valid && (execute_if.ex_type == `EX_MUL); - wire mul_stall = mul_req_if.valid && ~mul_req_if.ready; + wire mul_req_ready; - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), - .R (1) - ) mul_pipe ( + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)) + ) mul_buffer ( .clk (clk), .reset (reset), - .stall (mul_stall), - .flush (1'b0), - .data_in ({mul_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({mul_req_if.valid, mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data}) + .valid_in (mul_req_valid), + .ready_in (mul_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), + .data_out ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data}), + .valid_out (mul_req_if.valid), + .ready_out (mul_req_if.ready) ); `endif @@ -103,18 +108,19 @@ module VX_instr_demux ( `ifdef EXT_F_ENABLE wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU); - wire fpu_stall = fpu_req_if.valid && ~fpu_req_if.ready; + wire fpu_req_ready; - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), - .R (1) - ) fpu_pipe ( + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)) + ) fpu_buffer ( .clk (clk), .reset (reset), - .stall (fpu_stall), - .flush (1'b0), - .data_in ({fpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({fpu_req_if.valid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}) + .valid_in (fpu_req_valid), + .ready_in (fpu_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), + .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), + .valid_out (fpu_req_if.valid), + .ready_out (fpu_req_if.ready) ); `else `UNUSED_VAR (gpr_rsp_if.rs3_data) @@ -123,30 +129,31 @@ module VX_instr_demux ( // gpu unit wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU); - wire gpu_stall = gpu_req_if.valid && ~gpu_req_if.ready; + wire gpu_req_ready; - VX_generic_register #( - .N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)), - .R (1) - ) gpu_pipe ( + VX_skid_buffer #( + .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)) + ) gpu_buffer ( .clk (clk), .reset (reset), - .stall (gpu_stall), - .flush (1'b0), - .data_in ({gpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), - .data_out ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}) + .valid_in (gpu_req_valid), + .ready_in (gpu_req_ready), + .data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), + .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), + .valid_out (gpu_req_if.valid), + .ready_out (gpu_req_if.ready) ); // can take next request? - assign execute_if.ready = (!alu_stall && (execute_if.ex_type == `EX_ALU)) - || (!lsu_stall && (execute_if.ex_type == `EX_LSU)) - || (!csr_stall && (execute_if.ex_type == `EX_CSR)) + assign execute_if.ready = (alu_req_ready && (execute_if.ex_type == `EX_ALU)) + || (lsu_req_ready && (execute_if.ex_type == `EX_LSU)) + || (csr_req_ready && (execute_if.ex_type == `EX_CSR)) `ifdef EXT_M_ENABLE - || (!mul_stall && (execute_if.ex_type == `EX_MUL)) + || (mul_req_ready && (execute_if.ex_type == `EX_MUL)) `endif `ifdef EXT_F_ENABLE - || (!fpu_stall && (execute_if.ex_type == `EX_FPU)) + || (fpu_req_ready && (execute_if.ex_type == `EX_FPU)) `endif - || (!gpu_stall && (execute_if.ex_type == `EX_GPU)); + || (gpu_req_ready && (execute_if.ex_type == `EX_GPU)); endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_fdiv.sv b/hw/rtl/fp_cores/altera/acl_fdiv.sv index c6c73008..acba3a52 100644 --- a/hw/rtl/fp_cores/altera/acl_fdiv.sv +++ b/hw/rtl/fp_cores/altera/acl_fdiv.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_fdiv -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_fsqrt.sv b/hw/rtl/fp_cores/altera/acl_fsqrt.sv index 165effd6..84241c6d 100644 --- a/hw/rtl/fp_cores/altera/acl_fsqrt.sv +++ b/hw/rtl/fp_cores/altera/acl_fsqrt.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_fsqrt -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_ftoi.sv b/hw/rtl/fp_cores/altera/acl_ftoi.sv index e800b01d..404dba69 100644 --- a/hw/rtl/fp_cores/altera/acl_ftoi.sv +++ b/hw/rtl/fp_cores/altera/acl_ftoi.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_ftoi -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_ftou.sv b/hw/rtl/fp_cores/altera/acl_ftou.sv index cd5de555..b182e8e9 100644 --- a/hw/rtl/fp_cores/altera/acl_ftou.sv +++ b/hw/rtl/fp_cores/altera/acl_ftou.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_ftou -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_itof.sv b/hw/rtl/fp_cores/altera/acl_itof.sv index 5e6a74aa..2982444d 100644 --- a/hw/rtl/fp_cores/altera/acl_itof.sv +++ b/hw/rtl/fp_cores/altera/acl_itof.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_itof -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/fp_cores/altera/acl_utof.sv b/hw/rtl/fp_cores/altera/acl_utof.sv index 4b404625..21812e1f 100644 --- a/hw/rtl/fp_cores/altera/acl_utof.sv +++ b/hw/rtl/fp_cores/altera/acl_utof.sv @@ -16,7 +16,7 @@ // --------------------------------------------------------------------------- // SystemVerilog created from acl_utof -// SystemVerilog created on Wed Sep 2 07:11:09 2020 +// SystemVerilog created on Wed Dec 9 01:17:51 2020 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index e8b58529..3dc6f2b6 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -2,7 +2,8 @@ module VX_skid_buffer #( parameter DATAW = 1, - parameter PASSTHRU = 0 + parameter PASSTHRU = 0, + parameter REGISTER = 0 ) ( input wire clk, input wire reset, @@ -25,6 +26,24 @@ module VX_skid_buffer #( assign data_out = data_in; assign ready_in = ready_out; + end if (REGISTER) begin + + wire stall = valid_out && ~ready_out; + + VX_generic_register #( + .N (1 + DATAW), + .R (1) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .data_in ({valid_in, data_in}), + .data_out ({valid_out, data_out}) + ); + + assign ready_in = ~stall; + end else begin reg [DATAW-1:0] data_out_r; diff --git a/hw/syn/quartus/project.sdc b/hw/syn/quartus/project.sdc index a8170852..59686a41 100644 --- a/hw/syn/quartus/project.sdc +++ b/hw/syn/quartus/project.sdc @@ -1,6 +1,6 @@ set_time_format -unit ns -decimal_places 3 -create_clock -name {clk} -period "220 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] +create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] derive_pll_clocks -create_base_clocks derive_clock_uncertainty