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opae rtl fixes

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This commit is contained in:
Blaise Tine
2020-06-01 23:06:13 -07:00
parent 16d5a8a09c
commit e01c411b20
16 changed files with 192 additions and 121 deletions
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1
hw/rtl/VX_define.vh
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@@ -48,6 +48,7 @@
`define CLOG2(x) $clog2(x)
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1)
`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1))))
`define MIN(x, y) ((x < y) ? (x) : (y))
`define MAX(x, y) ((x > y) ? (x) : (y))

2
hw/rtl/VX_lsu_unit.v
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@@ -70,7 +70,7 @@ module VX_lsu_unit #(
for (i = 0; i < `NUM_THREADS; ++i) begin
assign mem_req_addr[i] = use_address[i][31:2];
assign mem_req_offset[i] = {3'b0, use_address[i][1:0]} << 3;
assign mem_req_offset[i] = (5'(use_address[i][1:0])) << 3;
assign mem_req_byteen[i] = (wmask << use_address[i][1:0]);
assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]);
end

2
hw/rtl/Vortex.v
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@@ -123,7 +123,7 @@ module Vortex #(
assign io_req_tag = io_core_req_if.core_req_tag[0];
assign io_core_req_if.core_req_ready = io_req_ready;
assign io_core_rsp_if.core_rsp_valid = {{`NUM_THREADS-1{1'b0}}, io_rsp_valid};
assign io_core_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign io_core_rsp_if.core_rsp_data[0] = io_rsp_data;
assign io_core_rsp_if.core_rsp_tag = io_rsp_tag;
assign io_rsp_ready = io_core_rsp_if.core_rsp_ready;

16
hw/rtl/cache/VX_bank.v vendored
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@@ -718,12 +718,12 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
/*if (core_req_valid && core_req_ready) begin
if (core_req_valid && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
@@ -733,21 +733,21 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
/*if (snp_req_valid && snp_req_ready) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end
end
end else begin
always_ff @(posedge clk) begin
/*if ((|core_req_valid) && core_req_ready) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
@@ -757,12 +757,12 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
/*if (snp_req_valid && snp_req_ready) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end
end
end
`endif

3
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -46,6 +46,7 @@ module VX_cache_core_rsp_merge #(
assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index];
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
@@ -60,6 +61,8 @@ module VX_cache_core_rsp_merge #(
end else begin
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]

2
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -97,7 +97,7 @@ module VX_snp_forwarder #(
always @(posedge clk) begin
if (reset) begin
fwdin_sel <= 0;
end else begin
end else if (NUM_REQUESTS > 1) begin
fwdin_sel <= fwdin_sel + 1;
end
end

2
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -136,7 +136,7 @@ module VX_tag_data_access #(
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE; // Dirty only applies in Dcache
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1];

3
hw/rtl/cache/VX_tag_data_structure.v vendored
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@@ -33,7 +33,7 @@ module VX_tag_data_structure #(
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_COUNT-1:0] dirty;
reg [`BANK_LINE_COUNT-1:0] valid;
assign read_valid = valid [read_addr];
@@ -49,6 +49,7 @@ module VX_tag_data_structure #(
if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0;
dirty[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (do_write) begin

24
hw/rtl/libs/VX_generic_queue.v
View File

@@ -15,6 +15,8 @@ module VX_generic_queue #(
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
);
`STATIC_ASSERT(0 == SIZE || `ISPOW2(SIZE), "must be 0 or power of 2!");
if (SIZE == 0) begin
assign empty = 1;
@@ -88,6 +90,7 @@ module VX_generic_queue #(
if (writing) begin
data[wr_ptr_a] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
size_r <= size_r + 1;
end
@@ -120,16 +123,17 @@ module VX_generic_queue #(
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
empty_r <= 1;
full_r <= 0;
size_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
empty_r <= 0;
if (size_r == SIZE-1) begin
@@ -140,15 +144,17 @@ module VX_generic_queue #(
end
if (reading) begin
rd_ptr_r <= rd_ptr_next_r;
if (SIZE == 2) begin
rd_ptr_next_r <= ~rd_ptr_next_r;
end else if (SIZE > 2) begin
rd_ptr_r <= rd_ptr_next_r;
if (SIZE > 2) begin
rd_ptr_next_r <= rd_ptr_r + 2;
end else begin // (SIZE == 2);
rd_ptr_next_r <= ~rd_ptr_next_r;
end
if (!writing) begin
if (size_r == 1) begin
assert(rd_ptr_next_r == wr_ptr_r);
empty_r <= 1;
end;
full_r <= 0;
@@ -156,7 +162,9 @@ module VX_generic_queue #(
end
end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
bypass_r <= writing
&& (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
end