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FPU DPI fallback

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This commit is contained in:
Blaise Tine
2020-08-31 09:19:55 -04:00
parent 0a0b28aac0
commit df711986bc
29 changed files with 1147 additions and 1329 deletions
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81
hw/rtl/fp_cores/altera/VX_fp_add.v
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`include "VX_define.vh"
module VX_fp_add #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(dataa[i]),
.ay(datab[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,enable}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result[i]),
.chainout()
);
defparam mac_fp_wys.operation_mode = "sp_add";
defparam mac_fp_wys.use_chainin = "false";
defparam mac_fp_wys.adder_subtract = "false";
defparam mac_fp_wys.ax_clock = "0";
defparam mac_fp_wys.ay_clock = "0";
defparam mac_fp_wys.az_clock = "none";
defparam mac_fp_wys.output_clock = "0";
defparam mac_fp_wys.accumulate_clock = "none";
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
defparam mac_fp_wys.accum_pipeline_clock = "none";
defparam mac_fp_wys.mult_pipeline_clock = "none";
defparam mac_fp_wys.adder_input_clock = "0";
defparam mac_fp_wys.accum_adder_clock = "none";
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

50
hw/rtl/fp_cores/altera/VX_fp_div.v
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`include "VX_define.vh"
module VX_fp_div #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_div fdiv (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.b (datab[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FDIV)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

48
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
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`include "VX_define.vh"
module VX_fp_ftoi #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftoi ftoi (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOI)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

48
hw/rtl/fp_cores/altera/VX_fp_ftou.v
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`include "VX_define.vh"
module VX_fp_ftou #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftou ftou (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOU)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

48
hw/rtl/fp_cores/altera/VX_fp_itof.v
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`include "VX_define.vh"
module VX_fp_itof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_itof itof (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_ITOF)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

146
hw/rtl/fp_cores/altera/VX_fp_madd.v
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`include "VX_define.vh"
module VX_fp_madd #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(datac[i]),
.ay(datab[i]),
.az(dataa[i]),
.clk({2'b00,clk}),
.ena({2'b11,enable0}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result_st0[i]),
.chainout()
);
defparam mac_fp_wys0.operation_mode = "sp_mult_add";
defparam mac_fp_wys0.use_chainin = "false";
defparam mac_fp_wys0.adder_subtract = "false";
defparam mac_fp_wys0.ax_clock = "0";
defparam mac_fp_wys0.ay_clock = "0";
defparam mac_fp_wys0.az_clock = "0";
defparam mac_fp_wys0.output_clock = "0";
defparam mac_fp_wys0.accumulate_clock = "none";
defparam mac_fp_wys0.ax_chainin_pl_clock = "0";
defparam mac_fp_wys0.accum_pipeline_clock = "none";
defparam mac_fp_wys0.mult_pipeline_clock = "0";
defparam mac_fp_wys0.adder_input_clock = "0";
defparam mac_fp_wys0.accum_adder_clock = "none";
twentynm_fp_mac mac_fp_wys1 (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(32'h0),
.ay(result_st0[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,enable1}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result_st1[i]),
.chainout()
);
defparam mac_fp_wys1.operation_mode = "sp_add";
defparam mac_fp_wys1.use_chainin = "false";
defparam mac_fp_wys1.adder_subtract = "true";
defparam mac_fp_wys1.ax_clock = "0";
defparam mac_fp_wys1.ay_clock = "0";
defparam mac_fp_wys1.az_clock = "none";
defparam mac_fp_wys1.output_clock = "0";
defparam mac_fp_wys1.accumulate_clock = "none";
defparam mac_fp_wys1.ax_chainin_pl_clock = "none";
defparam mac_fp_wys1.accum_pipeline_clock = "none";
defparam mac_fp_wys1.mult_pipeline_clock = "none";
defparam mac_fp_wys1.adder_input_clock = "0";
defparam mac_fp_wys1.accum_adder_clock = "none";
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
.reset(reset),
.enable(enable0),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),
.reset(reset),
.enable(enable1),
.in({out_tag_st0, in_valid_st0}),
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

146
hw/rtl/fp_cores/altera/VX_fp_msub.v
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@@ -1,146 +0,0 @@
`include "VX_define.vh"
module VX_fp_msub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(datac[i]),
.ay(datab[i]),
.az(dataa[i]),
.clk({2'b00,clk}),
.ena({2'b11,enable0}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result_st0[i]),
.chainout()
);
defparam mac_fp_wys0.operation_mode = "sp_mult_add";
defparam mac_fp_wys0.use_chainin = "false";
defparam mac_fp_wys0.adder_subtract = "true";
defparam mac_fp_wys0.ax_clock = "0";
defparam mac_fp_wys0.ay_clock = "0";
defparam mac_fp_wys0.az_clock = "0";
defparam mac_fp_wys0.output_clock = "0";
defparam mac_fp_wys0.accumulate_clock = "none";
defparam mac_fp_wys0.ax_chainin_pl_clock = "0";
defparam mac_fp_wys0.accum_pipeline_clock = "none";
defparam mac_fp_wys0.mult_pipeline_clock = "0";
defparam mac_fp_wys0.adder_input_clock = "0";
defparam mac_fp_wys0.accum_adder_clock = "none";
twentynm_fp_mac mac_fp_wys1 (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(32'h0),
.ay(result_st0[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,enable1}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result_st1[i]),
.chainout()
);
defparam mac_fp_wys1.operation_mode = "sp_add";
defparam mac_fp_wys1.use_chainin = "false";
defparam mac_fp_wys1.adder_subtract = "true";
defparam mac_fp_wys1.ax_clock = "0";
defparam mac_fp_wys1.ay_clock = "0";
defparam mac_fp_wys1.az_clock = "none";
defparam mac_fp_wys1.output_clock = "0";
defparam mac_fp_wys1.accumulate_clock = "none";
defparam mac_fp_wys1.ax_chainin_pl_clock = "none";
defparam mac_fp_wys1.accum_pipeline_clock = "none";
defparam mac_fp_wys1.mult_pipeline_clock = "none";
defparam mac_fp_wys1.adder_input_clock = "0";
defparam mac_fp_wys1.accum_adder_clock = "none";
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
.reset(reset),
.enable(enable0),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),
.reset(reset),
.enable(enable1),
.in({out_tag_st0, in_valid_st0}),
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

81
hw/rtl/fp_cores/altera/VX_fp_mul.v
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@@ -1,81 +0,0 @@
`include "VX_define.vh"
module VX_fp_mul #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(),
.ay(datab[i]),
.az(dataa[i]),
.clk({2'b00,clk}),
.ena({2'b11,enable}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result[i]),
.chainout()
);
defparam mac_fp_wys.operation_mode = "sp_mult";
defparam mac_fp_wys.use_chainin = "false";
defparam mac_fp_wys.adder_subtract = "false";
defparam mac_fp_wys.ax_clock = "none";
defparam mac_fp_wys.ay_clock = "0";
defparam mac_fp_wys.az_clock = "0";
defparam mac_fp_wys.output_clock = "0";
defparam mac_fp_wys.accumulate_clock = "none";
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
defparam mac_fp_wys.accum_pipeline_clock = "none";
defparam mac_fp_wys.mult_pipeline_clock = "0";
defparam mac_fp_wys.adder_input_clock = "none";
defparam mac_fp_wys.accum_adder_clock = "none";
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

48
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
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@@ -1,48 +0,0 @@
`include "VX_define.vh"
module VX_fp_sqrt #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_sqrt fsqrt (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FSQRT)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

81
hw/rtl/fp_cores/altera/VX_fp_sub.v
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@@ -1,81 +0,0 @@
`include "VX_define.vh"
module VX_fp_sub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
.chainin_overflow(),
.chainin_invalid(),
.chainin_underflow(),
.chainin_inexact(),
.ax(dataa[i]),
.ay(datab[i]),
.az(),
.clk({2'b00,clk}),
.ena({2'b11,enable}),
.aclr(2'b00),
.chainin(),
// outputs
.overflow(),
.invalid(),
.underflow(),
.inexact(),
.chainout_overflow(),
.chainout_invalid(),
.chainout_underflow(),
.chainout_inexact(),
.resulta(result[i]),
.chainout()
);
defparam mac_fp_wys.operation_mode = "sp_add";
defparam mac_fp_wys.use_chainin = "false";
defparam mac_fp_wys.adder_subtract = "true";
defparam mac_fp_wys.ax_clock = "0";
defparam mac_fp_wys.ay_clock = "0";
defparam mac_fp_wys.az_clock = "none";
defparam mac_fp_wys.output_clock = "0";
defparam mac_fp_wys.accumulate_clock = "none";
defparam mac_fp_wys.ax_chainin_pl_clock = "none";
defparam mac_fp_wys.accum_pipeline_clock = "none";
defparam mac_fp_wys.mult_pipeline_clock = "none";
defparam mac_fp_wys.adder_input_clock = "0";
defparam mac_fp_wys.accum_adder_clock = "none";
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

48
hw/rtl/fp_cores/altera/VX_fp_utof.v
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@@ -1,48 +0,0 @@
`include "VX_define.vh"
module VX_fp_utof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < LANES; i++) begin
acl_fp_utof utof (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_UTOF)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

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hw/rtl/fp_cores/altera/dspba_delay_ver.sv Normal file
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// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing device programming or simulation files), and
// any associated documentation or information are expressly subject to the
// terms and conditions of the Intel FPGA Software License Agreement,
// Intel MegaCore Function License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for the sole
// purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module dspba_delay_ver
#(
parameter width = 8,
parameter depth = 1,
parameter reset_high = 1'b1,
parameter reset_kind = "ASYNC"
) (
input clk,
input aclr,
input ena,
input [width-1:0] xin,
output [width-1:0] xout
);
wire reset;
reg [width-1:0] delays [depth-1:0];
assign reset = aclr ^ reset_high;
generate
if (depth > 0)
begin
genvar i;
for (i = 0; i < depth; ++i)
begin : delay_block
if (reset_kind == "ASYNC")
begin : sync_reset
always @ (posedge clk or negedge reset)
begin: a
if (!reset) begin
delays[i] <= 0;
end else begin
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
if (reset_kind == "SYNC")
begin : async_reset
always @ (posedge clk)
begin: a
if (!reset) begin
delays[i] <= 0;
end else begin
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
if (reset_kind == "NONE")
begin : no_reset
always @ (posedge clk)
begin: a
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
assign xout = delays[depth - 1];
end else begin
assign xout = xin;
end
endgenerate
endmodule

392
hw/rtl/fp_cores/altera/dspba_library_ver.sv
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// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing device programming or simulation files), and
// any associated documentation or information are expressly subject to the
// terms and conditions of the Intel FPGA Software License Agreement,
// Intel MegaCore Function License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for the sole
// purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module dspba_delay_ver
#(
parameter width = 8,
parameter depth = 1,
parameter reset_high = 1'b1,
parameter reset_kind = "ASYNC"
) (
input clk,
input aclr,
input ena,
input [width-1:0] xin,
output [width-1:0] xout
);
wire reset;
reg [width-1:0] delays [depth-1:0];
assign reset = aclr ^ reset_high;
generate
if (depth > 0)
begin
genvar i;
for (i = 0; i < depth; ++i)
begin : delay_block
if (reset_kind == "ASYNC")
begin : sync_reset
always @ (posedge clk or negedge reset)
begin: a
if (!reset) begin
delays[i] <= 0;
end else begin
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
if (reset_kind == "SYNC")
begin : async_reset
always @ (posedge clk)
begin: a
if (!reset) begin
delays[i] <= 0;
end else begin
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
if (reset_kind == "NONE")
begin : no_reset
always @ (posedge clk)
begin: a
if (ena) begin
if (i > 0) begin
delays[i] <= delays[i - 1];
end else begin
delays[i] <= xin;
end
end
end
end
end
assign xout = delays[depth - 1];
end else begin
assign xout = xin;
end
endgenerate
endmodule
//------------------------------------------------------------------------------
module dspba_sync_reg_ver
#(
parameter width1 = 8,
parameter width2 = 8,
parameter depth = 2,
parameter pulse_multiplier = 1,
parameter counter_width = 8,
parameter init_value = 0,
parameter reset1_high = 1'b1,
parameter reset2_high = 1'b1,
parameter reset_kind = "ASYNC"
) (
input clk1,
input aclr1,
input [0 : 0] ena,
input [width1-1 : 0] xin,
output [width1-1 : 0] xout,
input clk2,
input aclr2,
output [width2-1 : 0] sxout
);
wire [width1-1 : 0] init_value_internal;
wire reset1;
wire reset2;
reg iclk_enable;
reg [width1-1 : 0] iclk_data;
reg [width2-1 : 0] oclk_data;
// For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
// For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-1 : 0] sync_regs;
wire oclk_enable;
wire ena_internal;
reg [counter_width-1 : 0] counter;
assign init_value_internal = init_value;
assign reset1 = aclr1 ^ reset1_high;
assign reset2 = aclr2 ^ reset2_high;
generate
if (pulse_multiplier == 1)
begin: no_multiplication
assign ena_internal = ena[0];
end
endgenerate
generate
if (pulse_multiplier > 1)
begin: multiplu_ena_pulse
if (reset_kind == "ASYNC")
begin: async_reset
always @ (posedge clk1 or negedge reset1)
begin
if (reset1 == 1'b0) begin
counter <= 0;
end else begin
if (counter > 0) begin
if (counter == pulse_multiplier - 1) begin
counter <= 0;
end else begin
counter <= counter + 2'd1;
end
end else begin
if (ena[0] == 1'b1) begin
counter <= 1;
end
end
end
end
end
if (reset_kind == "SYNC")
begin: sync_reset
always @ (posedge clk1)
begin
if (reset1 == 1'b0) begin
counter <= 0;
end else begin
if (counter > 0) begin
if (counter == pulse_multiplier - 1) begin
counter <= 0;
end else begin
counter <= counter + 2'd1;
end
end else begin
if (ena[0] == 1'b1) begin
counter <= 1;
end
end
end
end
end
if (reset_kind == "NONE")
begin: no_reset
always @ (posedge clk1)
begin
if (counter > 0) begin
if (counter == pulse_multiplier - 1) begin
counter <= 0;
end else begin
counter <= counter + 2'd1;
end
end else begin
if (ena[0] == 1'b1) begin
counter <= 1;
end
end
end
end
assign ena_internal = counter > 0 ? 1'b1 : ena[0];
end
endgenerate
assign oclk_enable = sync_regs[depth - 1];
generate
if (reset_kind == "ASYNC")
begin: iclk_async_reset
always @ (posedge clk1 or negedge reset1)
begin
if (reset1 == 1'b0) begin
iclk_data <= init_value_internal;
iclk_enable <= 1'b0;
end else begin
iclk_enable <= ena_internal;
if (ena[0] == 1'b1) begin
iclk_data <= xin;
end
end
end
end
if (reset_kind == "SYNC")
begin: iclk_sync_reset
always @ (posedge clk1)
begin
if (reset1 == 1'b0) begin
iclk_data <= init_value_internal;
iclk_enable <= 1'b0;
end else begin
iclk_enable <= ena_internal;
if (ena[0] == 1'b1) begin
iclk_data <= xin;
end
end
end
end
if (reset_kind == "NONE")
begin: iclk_no_reset
always @ (posedge clk1)
begin
iclk_enable <= ena_internal;
if (ena[0] == 1'b1) begin
iclk_data <= xin;
end
end
end
endgenerate
generate
genvar i;
for (i = 0; i < depth; ++i)
begin: sync_regs_block
if (reset_kind == "ASYNC")
begin: sync_reg_async_reset
always @ (posedge clk2 or negedge reset2) begin
if (reset2 == 1'b0) begin
sync_regs[i] <= 1'b0;
end else begin
if (i > 0) begin
sync_regs[i] <= sync_regs[i - 1];
end else begin
sync_regs[i] <= iclk_enable;
end
end
end
end
if (reset_kind == "SYNC")
begin: sync_reg_sync_reset
always @ (posedge clk2) begin
if (reset2 == 1'b0) begin
sync_regs[i] <= 1'b0;
end else begin
if (i > 0) begin
sync_regs[i] <= sync_regs[i - 1];
end else begin
sync_regs[i] <= iclk_enable;
end
end
end
end
if (reset_kind == "NONE")
begin: sync_reg_no_reset
always @ (posedge clk2) begin
if (i > 0) begin
sync_regs[i] <= sync_regs[i - 1];
end else begin
sync_regs[i] <= iclk_enable;
end
end
end
end
endgenerate
generate
if (reset_kind == "ASYNC")
begin: oclk_async_reset
always @ (posedge clk2 or negedge reset2)
begin
if (reset2 == 1'b0) begin
oclk_data <= init_value_internal[width2-1 : 0];
end else begin
if (oclk_enable == 1'b1) begin
oclk_data <= iclk_data[width2-1 : 0];
end
end
end
end
if (reset_kind == "SYNC")
begin: oclk_sync_reset
always @ (posedge clk2)
begin
if (reset2 == 1'b0) begin
oclk_data <= init_value_internal[width2-1 : 0];
end else begin
if (oclk_enable == 1'b1) begin
oclk_data <= iclk_data[width2-1 : 0];
end
end
end
end
if (reset_kind == "NONE")
begin: oclk_no_reset
always @ (posedge clk2)
begin
if (oclk_enable == 1'b1) begin
oclk_data <= iclk_data[width2-1 : 0];
end
end
end
endgenerate
assign xout = iclk_data;
assign sxout = oclk_data;
endmodule
//------------------------------------------------------------------------------
module dspba_pipe
#(
parameter num_bits = 8,
parameter num_stages = 0,
parameter init_value = 1'bx
) (
input clk,
input [num_bits-1:0] d,
output [num_bits-1:0] q
);
logic [num_bits-1:0] init_stage = { num_bits { init_value } };
generate
if (num_stages > 0)
begin
reg [num_bits-1:0] stage_array[num_stages-1:0];
genvar i;
for (i = 0; i < num_stages; ++i)
begin : g_pipe
always @ (posedge clk) begin
if (i>0) begin
stage_array[i] <= stage_array[i-1];
end else begin
stage_array[i] <= d;
end
end
end
initial begin
stage_array = '{ num_stages { init_stage } };
end
assign q = stage_array[num_stages-1];
end else begin
assign q = d;
end
endgenerate
endmodule