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Don't print from mem_scheduler in reset

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Hansung Kim
2024-06-09 21:07:22 -07:00
parent 5d5e4a468c
commit de10d5a957
1 changed files with 59 additions and 55 deletions
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8
hw/rtl/libs/VX_mem_scheduler.sv
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@@ -532,7 +532,8 @@ module VX_mem_scheduler #(
`ifndef NDEBUG `ifndef NDEBUG
wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s; wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
always @(posedge clk) begin always @(negedge clk) begin
if (!reset) begin
if (req_valid && req_ready) begin if (req_valid && req_ready) begin
if (req_rw) begin if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -572,8 +573,10 @@ module VX_mem_scheduler #(
`TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid)); `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid));
end end
end end
end
`else `else
always @(posedge clk) begin always @(negedge clk) begin
if (!reset) begin
if (req_valid && req_ready) begin if (req_valid && req_ready) begin
if (req_rw) begin if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -594,6 +597,7 @@ module VX_mem_scheduler #(
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0])); `TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0]));
end end
end end
end
`endif `endif
endmodule endmodule