pipeline refactoring

hw/rtl/libs/VX_generic_register.v

@@ -20,12 +20,10 @@ module VX_generic_register #(
         reg [(N-1):0] value;
 
         always @(posedge clk) begin
-            if (reset) begin
+            if (reset || flush) begin
                 value <= N'(0);
             end else if (~stall) begin
                 value <= in;
-            end else if (flush) begin
-                value <= N'(0);
             end
         end
 

hw/rtl/libs/VX_generic_stack.v

@@ -1,7 +1,7 @@
 
 module VX_generic_stack #(
-    parameter WIDTH = 40,
-    parameter DEPTH = 2
+    parameter WIDTH = 1,
+    parameter DEPTH = 1
 ) (
     input  wire              clk,
     input  wire              reset,