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pipeline refactoring

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This commit is contained in:
Blaise Tine
2020-07-21 05:22:47 -04:00
parent e2100e9e87
commit dc7efbcfb4
31 changed files with 1437 additions and 6038 deletions
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8
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -11,14 +11,14 @@ interface VX_alu_req_if ();
wire [`ALU_BITS-1:0] alu_op;
wire [`WB_BITS-1:0] wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [31:0] offset;
wire [31:0] next_PC;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire [31:0] next_PC;
wire ready;

32
hw/rtl/interfaces/VX_execute_if.v
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@@ -1,32 +0,0 @@
`ifndef VX_EXECUTE_IF
`define VX_EXECUTE_IF
`include "VX_define.vh"
interface VX_execute_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] instr_op;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [31:0] next_PC;
wire [`WB_BITS-1:0] wb;
wire alu_ready;
wire mul_ready;
wire lsu_ready;
wire csr_ready;
wire gpu_ready;
endinterface
`endif

13
hw/rtl/interfaces/VX_gpr_data_if.v Normal file
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@@ -0,0 +1,13 @@
`ifndef VX_GPR_DATA_IF
`define VX_GPR_DATA_IF
`include "VX_define.vh"
interface VX_gpr_data_if ();
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
endinterface
`endif

4
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -5,9 +5,9 @@
interface VX_ifetch_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -5,9 +5,9 @@
interface VX_ifetch_rsp_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] instr;
wire ready;

14
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -6,15 +6,19 @@
interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] curr_PC;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire [31:0] curr_PC;
wire rw;
wire [`BYTEEN_BITS-1:0] byteen;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire ready;
endinterface

20
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -5,19 +5,19 @@
interface VX_mul_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`MUL_BITS-1:0] mul_op;
wire [`WB_BITS-1:0] wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`MUL_BITS-1:0] mul_op;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire ready;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_wb_if.v
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@@ -6,9 +6,9 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NW_BITS-1:0] warp_num;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
endinterface