wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bug fixes - lkg build

Browse Source
This commit is contained in:
Blaise Tine
2021-08-01 19:21:37 -07:00
parent fd0d908a68
commit dc322894cd
13 changed files with 197 additions and 151 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
hw/rtl/tex_unit/VX_tex_addr.v
View File

@@ -5,8 +5,8 @@ module VX_tex_addr #(
parameter REQ_INFO_WIDTH = 1,
parameter NUM_REQS = 1
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// inputs
@@ -17,8 +17,8 @@ module VX_tex_addr #(
input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps,
input wire [`TEX_ADDR_BITS-1:0] req_baseaddr,
input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoffset,
input wire [1:0][NUM_REQS-1:0][`TEX_DIM_BITS-1:0] req_logdims,
input wire [NUM_REQS-1:0][`TEX_MIPOFF_BITS-1:0] req_mipoff,
input wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] req_logdims,
input wire [REQ_INFO_WIDTH-1:0] req_info,
output wire req_ready,
@@ -29,7 +29,7 @@ module VX_tex_addr #(
output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
output wire [`TEX_STRIDE_BITS-1:0] rsp_stride,
output wire [NUM_REQS-1:0][3:0][31:0] rsp_addr,
output wire [1:0][NUM_REQS-1:0][`BLEND_FRAC-1:0] rsp_blends,
output wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends,
output wire [REQ_INFO_WIDTH-1:0] rsp_info,
input wire rsp_ready
);
@@ -40,11 +40,11 @@ module VX_tex_addr #(
wire [NUM_REQS-1:0] tmask_s0;
wire [`TEX_FILTER_BITS-1:0] filter_s0;
wire [REQ_INFO_WIDTH-1:0] req_info_s0;
wire [1:0][NUM_REQS-1:0][31:0] coord_lo, coord_lo_s0;
wire [1:0][NUM_REQS-1:0][31:0] coord_hi, coord_hi_s0;
wire [NUM_REQS-1:0][1:0][31:0] coord_lo, coord_lo_s0;
wire [NUM_REQS-1:0][1:0][31:0] coord_hi, coord_hi_s0;
wire [`TEX_STRIDE_BITS-1:0] log_stride, log_stride_s0;
wire [NUM_REQS-1:0][31:0] mip_addr, mip_addr_s0;
wire [1:0][NUM_REQS-1:0][`TEX_DIM_BITS-1:0] log_dims_s0;
wire [NUM_REQS-1:0][1:0][`TEX_DIM_BITS-1:0] log_dims_s0;
wire [1:0][`TEX_WRAP_BITS-1:0] req_wraps_s0;
wire stall_out;
@@ -62,10 +62,10 @@ module VX_tex_addr #(
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < 2; ++j) begin
assign coord_lo[j][i] = req_filter ? (req_coords[j][i] - (`FIXED_HALF >> req_logdims[j][i])) : req_coords[j][i];
assign coord_hi[j][i] = req_filter ? (req_coords[j][i] + (`FIXED_HALF >> req_logdims[j][i])) : req_coords[j][i];
assign coord_lo[i][j] = req_filter ? (req_coords[j][i] - (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i];
assign coord_hi[i][j] = req_filter ? (req_coords[j][i] + (`FIXED_HALF >> req_logdims[i][j])) : req_coords[j][i];
end
assign mip_addr[i] = req_baseaddr + 32'(req_mipoffset[i]);
assign mip_addr[i] = req_baseaddr + 32'(req_mipoff[i]);
end
VX_pipe_register #(
@@ -81,8 +81,9 @@ module VX_tex_addr #(
// addresses generation
wire [1:0][NUM_REQS-1:0][`FIXED_INT-1:0] scaled_lo, scaled_hi;
wire [1:0][NUM_REQS-1:0][`BLEND_FRAC-1:0] blends;
wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_lo;
wire [NUM_REQS-1:0][1:0][`FIXED_INT-1:0] scaled_hi;
wire [NUM_REQS-1:0][1:0][`BLEND_FRAC-1:0] blends;
wire [NUM_REQS-1:0][3:0][31:0] addr;
for (genvar i = 0; i < NUM_REQS; ++i) begin
@@ -94,7 +95,7 @@ module VX_tex_addr #(
.CORE_ID (CORE_ID)
) tex_wrap_lo (
.wrap_i (req_wraps_s0[j]),
.coord_i (coord_lo_s0[j][i]),
.coord_i (coord_lo_s0[i][j]),
.coord_o (clamped_lo)
);
@@ -102,21 +103,21 @@ module VX_tex_addr #(
.CORE_ID (CORE_ID)
) tex_wrap_hi (
.wrap_i (req_wraps_s0[j]),
.coord_i (coord_hi_s0[j][i]),
.coord_i (coord_hi_s0[i][j]),
.coord_o (clamped_hi)
);
assign scaled_lo[j][i] = `FIXED_INT'(clamped_lo >> ((`FIXED_FRAC) - log_dims_s0[j][i]));
assign scaled_hi[j][i] = `FIXED_INT'(clamped_hi >> ((`FIXED_FRAC) - log_dims_s0[j][i]));
assign blends[j][i] = filter_s0 ? clamped_lo[`BLEND_FRAC-1:0] : `BLEND_FRAC'(0);
assign scaled_lo[i][j] = `FIXED_INT'(clamped_lo >> ((`FIXED_FRAC) - log_dims_s0[i][j]));
assign scaled_hi[i][j] = `FIXED_INT'(clamped_hi >> ((`FIXED_FRAC) - log_dims_s0[i][j]));
assign blends[i][j] = filter_s0 ? clamped_lo[`BLEND_FRAC-1:0] : `BLEND_FRAC'(0);
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign addr[i][0] = mip_addr_s0[i] + (32'(scaled_lo[0][i]) + (32'(scaled_lo[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
assign addr[i][1] = mip_addr_s0[i] + (32'(scaled_hi[0][i]) + (32'(scaled_lo[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
assign addr[i][2] = mip_addr_s0[i] + (32'(scaled_lo[0][i]) + (32'(scaled_hi[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
assign addr[i][3] = mip_addr_s0[i] + (32'(scaled_hi[0][i]) + (32'(scaled_hi[1][i]) << log_dims_s0[0][i])) << log_stride_s0;
assign addr[i][0] = mip_addr_s0[i] + (32'(scaled_lo[i][0]) + (32'(scaled_lo[i][1]) << log_dims_s0[i][0])) << log_stride_s0;
assign addr[i][1] = mip_addr_s0[i] + (32'(scaled_hi[i][0]) + (32'(scaled_lo[i][1]) << log_dims_s0[i][0])) << log_stride_s0;
assign addr[i][2] = mip_addr_s0[i] + (32'(scaled_lo[i][0]) + (32'(scaled_hi[i][1]) << log_dims_s0[i][0])) << log_stride_s0;
assign addr[i][3] = mip_addr_s0[i] + (32'(scaled_hi[i][0]) + (32'(scaled_hi[i][1]) << log_dims_s0[i][0])) << log_stride_s0;
end
assign stall_out = rsp_valid && ~rsp_ready;