fixed pipe register reset issue in synthesis

2021-01-01 14:54:18 -08:00
parent c5cf494e72
commit da9649c2a3
2 changed files with 7 additions and 10 deletions
--- a/hw/rtl/VX_cluster.v
+++ b/hw/rtl/VX_cluster.v
@@ -67,20 +67,14 @@ module VX_cluster #(
    wire [`NUM_CORES-1:0]                        per_core_busy;
    wire [`NUM_CORES-1:0]                        per_core_ebreak;

-    for (genvar i = 0; i < `NUM_CORES; i++) begin    
-    
-        reg core_reset;
-        always @(posedge clk) begin
-            core_reset <= reset;
-        end
-
+    for (genvar i = 0; i < `NUM_CORES; i++) begin
        VX_core #(
            .CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
        ) core (
            `SCOPE_BIND_VX_cluster_core(i)

            .clk            (clk),
-            .reset          (core_reset),
+            .reset          (reset),

            .dram_req_valid (per_core_dram_req_valid[i]),
            .dram_req_rw    (per_core_dram_req_rw   [i]),